LPDDR4 Interface without ECC Chip Select Routing

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

This Figure shows the chip select (CS) routing for the LPDDR4 interface without ECC.

Figure 2-39: Chip Select Routing for LPDDR4 without ECC
X-Ref Target - Figure 2-39

Table: Impedance, Length, and Spacing Guidelines for Chip Select in LPDDR4 Interface without ECC shows the impedance, length, and spacing guidelines for chip select in the LPDDR4 interface without ECC.

Table 2-41: Impedance, Length, and Spacing Guidelines for Chip Select in LPDDR4 Interface without ECC
Parameter	L0 (Device Breakout)	L1 (Main PCB)	L2 (DRAM Breakout)	L3	Units
Trace type	Stripline	Stripline	Stripline	Stripline	–
Single-ended impedance Z₀	50±10%	39±10%	52±10%	50±10%	W
Trace width	4.0	6.0	3.5	4.0	mil
Trace length	0.0~0.55/0.95⁽¹⁾	£4.0	£0.3	£0.3	inches
Spacing to clock signals (minimum)	8.0	20	8.0	20	mil
Spacing to other group signals (minimum)	8.0	30	8.0	30	mil
Maximum PCB via count	3				–
Notes: 1.See item 2 in General Memory Routing Guidelines.