LPDDR4 with ECC Address/Command and Control Routing (CA_A)

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

This Figure shows the CA_A address/command routing for the LPDDR4 interface with ECC. The RTT termination exists to terminate the fly-by route.

Figure 2-43:      CA_A Address/Command Routing for LPDDR4 with ECC

X-Ref Target - Figure 2-43

ug583_c8_09.jpg

Table: Impedance, Length, and Spacing Guidelines for CA_A Address/Command Signals in LPDDR4 Interface with ECC shows the impedance, length, and spacing guidelines for CA_A address/command signals in the LPDDR4 interface with ECC.

Table 2-50:      Impedance, Length, and Spacing Guidelines for CA_A Address/Command Signals in
LPDDR4 Interface with ECC

Parameter

L0
(Device Breakout)

L1
(Main PCB)

L2
(DRAM Breakout)

L3
(Stub)

Units

Trace type

Stripline

Stripline

Stripline

Stripline

Single-ended impedance Z0

50±10%

39±10%

52±10%

50±10%

W

Trace width

4.0

6.0

3.5

4.0

mil

Trace length

£0.55/0.95(1)

£4.0

£0.3

£0.5

inches

Spacing to addr/cmd (minimum)

4.0

6.0

4.0

6.0

mil

Spacing to clock signals (minimum)

8.0

20

8.0

20

mil

Spacing to other group signals (minimum)

8.0

30

8.0

30

mil

Maximum PCB via count

3

Notes:

1.See item 2 in General Memory Routing Guidelines.