This Figure shows the CK0 differential point-to-point routing for the LPDDR4 interface with ECC.
Table: Impedance, Length, and Spacing Guidelines for CK0 in LPDDR4 Interface with ECC shows the impedance, length, and spacing guidelines for CK0 in the LPDDR4 interface with ECC.
Parameter |
L0 |
L1 |
L2 |
L3 |
Units |
---|---|---|---|---|---|
Trace type |
Stripline |
Stripline |
Stripline |
Stripline |
– |
Clock differential impedance Zdiff |
86±10% |
76±10% |
88±10% |
93±10% |
W |
Trace width/space/width |
4.0/4.0/4.0 |
6.0/6.0/6.0 |
3.5/3.5/3.5 |
4.0/6.0/4.0 |
mil |
Trace length |
£0.55/0.95(1) |
£4.0 |
£0.3 |
£0.5 |
inches |
Spacing in addr/cmd/ctrl (minimum) |
8.0 |
20 |
8.0 |
20 |
mil |
Spacing to other group signals (minimum) |
8.0 |
30 |
8.0 |
30 |
mil |
Maximum PCB via count per signal |
3 |
– |
|||
Notes: 1.See item 2 in General Memory Routing Guidelines. |