LPDDR4 with ECC Chip Select Routing

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

This Figure shows the chip select (CS0/CS1) routing for the LPDDR4 interface with ECC. The R_TT termination exists to terminate the fly-by route.

Figure 2-45: CS0/CS1 Routing for LPDDR4 with ECC
X-Ref Target - Figure 2-45

Table: Impedance, Length, and Spacing Guidelines for CS0/CS1 in LPDDR4 Interface with ECC shows the impedance, length, and spacing guidelines for CS0/CS1 routing in the LPDDR4 interface with ECC.

Table 2-52: Impedance, Length, and Spacing Guidelines for CS0/CS1 in LPDDR4 Interface with ECC
Parameter	L0 (Device Breakout)	L1 (Main PCB)	L2 (DRAM Breakout)	L3 (Channel to Channel)	L4 (Chip to Chip)	L5 (Stub)	Units
Trace type	Stripline	Stripline	Stripline	Stripline	Stripline	Stripline	–
Single-ended impedance Z₀	50±10%	39±10%	52±10%	52±10%	52±10%	50±10%	W
Trace width	4.0	6.0	3.5	3.5	3.5	4.0	mil
Trace length	£0.55/0.95⁽¹⁾	£4.0	£0.3	£0.5	£1.5	£0.5	inches
Spacing to clock signals (minimum)	8.0	20	8.0	20	20	20	mil
Spacing to other group signals (minimum)	8.0	30	8.0	30	30	30	mil
Maximum PCB via count	4						–
Notes: 1.See item 2 in General Memory Routing Guidelines.