This Figure shows the clock enable (CKE0/CKE1) routing for the LPDDR4 interface with ECC.
Table: Impedance, Length, and Spacing Guidelines for CKE0/CKE1 in LPDDR4 Interface with ECC shows the impedance, length, and spacing guidelines for CKE0/CKE1 in the LPDDR4 interface with ECC.
Parameter |
L0 |
L1 |
L2 |
L3 |
L4 |
L5 |
Units |
---|---|---|---|---|---|---|---|
Trace type |
Stripline |
Stripline |
Stripline |
Stripline |
Stripline |
Stripline |
– |
Single-ended impedance Z0 |
50±10% |
39±10% |
52±10% |
52±10% |
52±10% |
50±10% |
W |
Trace width |
4.0 |
6.0 |
3.5 |
3.5 |
3.5 |
4.0 |
mil |
Trace length |
0.0~0.55/0.95(1) |
£4.0 |
£0.3 |
£0.5 |
£1.5 |
£0.5 |
inches |
Spacing to clock signals (minimum) |
8.0 |
20 |
8.0 |
20 |
20 |
20 |
mil |
Spacing to other group signals (minimum) |
8.0 |
30 |
8.0 |
30 |
30 |
30 |
mil |
Maximum PCB via count |
5 |
– |
|||||
Notes: 1.See item 2 in General Memory Routing Guidelines. |