LPDDR4 with ECC DQS Differential Point-to-Point Routing

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

This Figure shows the DQS point-to-point routing for the LPDDR4 interface with ECC.

Figure 2-50:      DQS Routing for LPDDR4 with ECC

X-Ref Target - Figure 2-50

ug583_c8_16.jpg

Table: Impedance, Length, and Spacing Guidelines for DQS in LPDDR4 Interface with ECC shows the impedance, length, and spacing guidelines for DQS in the LPDDR4 interface with ECC.

Table 2-57:      Impedance, Length, and Spacing Guidelines for DQS in LPDDR4 Interface with ECC

Parameter

L0
(Device Breakout)

L1
(Main PCB)

L2
(DRAM Breakout)

Units

Trace type

Stripline

Stripline

Stripline

Clock differential impedance Zdiff

86±10%

76±10%

88±10%

W

Trace width/space/width

4.0/4.0/4.0

6.0/6.0/6.0

3.5/3.5/3.5

mil

Trace length

£0.55/0.95(1)

£4.0

£0.3

inches

Spacing in addr/cmd/ctrl (minimum)

4.0

20

4.0

mil

Spacing to other group signals (minimum)

8.0

30

8.0

mil

Maximum PCB via count per signal

2

Notes:

1.See item 2 in General Memory Routing Guidelines.