This Figure shows the DQ point-to-point routing for the LPDDR4 interface with ECC.
Table: Impedance, Length, and Spacing Guidelines for DQ in LPDDR4 Interface with ECC shows the impedance, length, and spacing guidelines for DQ in the LPDDR4 interface with ECC.
|
Parameter |
L0 |
L1 |
L2 |
Units |
|---|---|---|---|---|
|
Trace type |
Stripline |
Stripline |
Stripline |
– |
|
Single-ended impedance Z0 |
50±10% |
39±10% |
52±10% |
W |
|
Trace width |
4.0 |
6.0 |
3.5 |
mil |
|
Trace length |
£0.55/0.95(1) |
£4.0 |
£0.3 |
inches |
|
Spacing in byte (including DQS) (minimum) |
4.0 |
8.0 |
4.0 |
mil |
|
Spacing byte to byte (minimum) |
8.0 |
20 |
4.0 |
mil |
|
Spacing to other group signals (minimum) |
8.0 |
30 |
8.0 |
mil |
|
Maximum PCB via count |
2 |
– |
||
|
Notes: 1.See item 2 in General Memory Routing Guidelines. |
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