LPDDR4 without ECC Data (DQ and DM) Point-to-Point Routing

UltraScale Architecture PCB Design User Guide (UG583)
Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

This Figure shows the DQ and DM point-to-point routing for the LPDDR4 interface without ECC.

Figure 2-42:      DQ and DM Routing for LPDDR4 without ECC

X-Ref Target - Figure 2-42

ug583_c8_07.jpg

Table: Impedance, Length, and Spacing Guidelines for DQ and DM in LPDDR4 Interface without ECC shows the impedance, length, and spacing guidelines for DQ and DM in the LPDDR4 interface without ECC.

Table 2-44:      Impedance, Length, and Spacing Guidelines for DQ and DM in LPDDR4 Interface without ECC

Parameter

L0
(Device Breakout)

L1
(Main PCB)

L2
(DRAM Breakout)

Units

Trace type

Stripline

Stripline

Stripline

–

Single-ended impedance Z0

50±10%

39±10%

52±10%

W

Trace width

4.0

6.0

3.5

mil

Trace length

£0.55/0.95(1)

£4.0

£0.3

inches

Spacing in byte (including DQS) (minimum)

4.0

8.0

4.0

mil

Spacing byte to byte (minimum)

8.0

30

8.0

mil

Spacing to other group signals (minimum)

8.0

20

8.0

mil

Maximum PCB via count

2

–

Notes:

1.See item 2 in General Memory Routing Guidelines.