LPDDR4 without ECC Length and Skew Constraints

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

The constraints requirement for each signal group in the LPDDR4 without ECC memory interface consists of two parts:

•Maximum length constraints

•Skew constraints

The maximum length constraints are shown in Table: LPDDR4 without ECC Maximum Length Constraints.

Table 2-45: LPDDR4 without ECC Maximum Length Constraints
Signal Group	Reference Figure	Maximum Length Constraints (inches)
Address/command P0+L0+L1+L2	This Figure	6.2
CS P0+L0+L1+L2+L3	This Figure	6.8
CKE P0+L0+L1+L2+L3	This Figure	7.9
Data signals P0+L0+L1+L2	This Figure	6.2

The skew constraints are listed in Table: LPDDR4 without ECC Skew Constraints.

Table 2-46: LPDDR4 without ECC Skew Constraints
Signal Group	Signal Segment	Skew Constraints (ps)	Skew Constraints (mil)
Address/command/control to CK (A) Address/command/control to CK (B)	MPSoC to memory device	±8	±47
Data (DQ/DM) to DQS (A) Data (DQ/DM) to DQS (B)	MPSoC to memory device	±5	±29
CK (A) to DQS0/1 (A) CK (B) to DQS0/1 (B)	MPSoC to memory device	–500 to 2500	–2950 to 14750
DQ/DM (slowest to fastest) (A) DQ/DM (slowest to fastest) (B)	MPSoC to memory device	5	29
CK_T and CK_C (A) CK_T and CK_C (B)	MPSoC to memory device	2	11
DQS_T and DQS_C (A) DQS_T and DQS_C (B)	MPSoC to memory device	2	11
Notes: 1.For skew specifications, refer to items 3–8 in General Memory Routing Guidelines. 2.The signal reset_n is not required to meet the skew constraints in this table.

IMPORTANT: FPGA package flight times must be included in both total length constraints and skew constraints. When minimum and maximum values are available for the package delay, use the midrange between the minimum and maximum values. Memory device package flight times do not need to be factored in because their variances have been accounted for in these guidelines.