LPDDR4 x32 with ECC Memory Interface Signals and Connections

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

The required signals for a x32 dual channel LPDDR4 single-rank with ECC interface are shown in Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 Single-Rank with ECC. The table shows how to connect the FPGA memory interface signals to the correct pins on the LPDDR4 devices, along with any required termination.

Table 2-47: Signal Connection Matrix for x32 Dual Channel LPDDR4 Single-Rank with ECC
FPGA Pins	LPDDR4 Pins MAIN DEVICE	LPDDR4 Pins ECC DEVICE	PCB Termination at Far End
Clock Signals
CK0_P CK0_N	CK_t_A CK_c_A		40W to GND 40W to GND
CK1_P CK1_N	CK_t_B CK_c_B	CK_t_A CK_c_A	40W to GND 40W to GND
Address and Command Signals
A[5:0]	CA[5:0]_A		40W to GND
A[15:10]	CA[5:0]_B	CA[5:0]_A	40W to GND
Control Signals (CKE, CS, and ODT ⁽¹⁾)
CKE0	CKE_A CKE_B	CKE_A	160W to V_DDQ/160W to GND
CS0	CS_A CS_B	CS_A	40W to GND
	ODT_CA_A	ODT_CA_A	Direct connect to GND
	ODT_CA_B		Direct connect to GND
Data Signals
DQ[15:0]	DQ[15:0]_A		None
DQ[31:16]	DQ[15:0]_B		None
DQ[71:64]		DQ[7:0]_A	None
DM0	DMI0_A		None
DM1	DMI1_A		None
DM2	DMI0_B		None
DM3	DMI1_B		None
DM8		DMI0_A	None
DQS0_P DQS0_N	DQS0_t_A DQS0_c_A		None
DQS1_P DQS1_N	DQS1_t_A DQS1_c_A		None
DQS2_P DQS2_N	DQS0_t_B DQS0_c_B		None
DQS3_P DQS3_N	DQS1_t_B DQS1_c_B		None
DQS8_P DQS8_N		DQS0_t_A DQS0_c_A	None
Reset
RESET_N	RESET_n	RESET_n	4.7 kW to GND
Notes: 1.The FPGA ODT pins should be left unconnected. The ODT pin(s) of the memory device should be directly connected as specified in this table. 2.Unused inputs to the LPDDR4 ECC device can be grounded through a common 100W resistor. 3.Each ZQ pin on the LPDDR4 devices should be individually tied to V_DDQ through a 240W resistor. 4.The ZQ pin on the FPGA should be tied to GND through a 240W resistor. 5.Actual signal list might vary based on configuration.

The required signals for a x32 dual channel LPDDR4 dual-rank with ECC interface are shown in Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 Dual-Rank with ECC. The table shows how to connect the FPGA memory interface signals to the correct pins on the LPDDR4 devices, along with any required termination.

Table 2-48: Signal Connection Matrix for x32 Dual Channel LPDDR4 Dual-Rank with ECC
FPGA Pins	LPDDR4 Pins Main Device	LPDDR4 Pins ECC Device	PCB Termination at Far End
Clock Signals
CK0_P CK0_N	CK_t_A CK_c_A		40W to GND 40W to GND
CK1_P CK1_N	CK_t_B CK_c_B	CK_t_A CK_c_A	40W to GND 40W to GND
Address and Command Signals
A[5:0]	CA[5:0]_A		40W to GND
A[15:10]	CA[5:0]_B	CA[5:0]_A	40W to GND
Control Signals (CKE, CS, and ODT ⁽¹⁾)
CKE0	CKE0_A CKE0_B	CKE0_A	160W to V_DDQ/160W to GND
CKE1	CKE1_A CKE1_B	CKE1_A	160W to V_DDQ/160W to GND
CS0	CS0_A CS0_B	CS0_A CS0_B	40W to GND
CS1	CS1_A CS1_B	CS1_A CS1_B	40W to GND
	ODT_CA_A	ODT_CA_A	Direct connect to GND
	ODT_CA_B		Direct connect to GND
Data Signals
DQ[15:0]	DQ[15:0]_A		None
DQ[31:16]	DQ[15:0]_B		None
DQ[71:64]		DQ[7:0]_A	None
DM0	DMI0_A		None
DM1	DMI1_A		None
DM2	DMI0_B		None
DM3	DMI1_B		None
DM8		DMI0_A	None
DQS0_P DQS0_N	DQS0_t_A DQS0_c_A		None
DQS1_P DQS1_N	DQS1_t_A DQS1_c_A		None
DQS2_P DQS2_N	DQS0_t_B DQS0_c_B		None
DQS3_P DQS3_N	DQS1_t_B DQS1_c_B		None
DQS8_P DQS8_N		DQS0_t_A DQS0_c_A	None
Reset
RESET_B	RESET_n	RESET_n	4.7 kW to GND
Notes: 1.The FPGA ODT pins should be left unconnected. The ODT pin(s) of the memory device should be directly connected as specified in this table. 2.Unused inputs to the LPDDR4 ECC device can be grounded through a common 100W resistor. 3.Each ZQ pin on the LPDDR4 devices should be individually tied to V_DDQ through a 240W resistor. 4.The ZQ pin on the FPGA should be tied to GND through a 240W resistor. 5.Actual signal list might vary based on configuration.