LVDS

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

This Figure shows how an LVDS, current mode logic (CML), or high-speed current steering logic (HCSL) oscillator is connected to a reference clock input of the PS-GTR transceiver.

Figure 4-6: Interfacing an LVDS, CML, or HCSL Oscillator to the Zynq UltraScale+ MPSoC PS-GTR Transceiver Reference Clock Input
X-Ref Target - Figure 4-6