LVPECL

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

This Figure shows how a low-voltage positive emitter-coupled logic (LVPECL) oscillator is connected to a reference clock input of the PS-GTR transceiver.

Figure 4-7:      Interfacing an LVPECL Oscillator to the Zynq UltraScale+ MPSoC PS-GTR Transceiver Reference Clock Input

X-Ref Target - Figure 4-7

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