Layer 1 (Top Layer) in BGA Area for DACs/ADCs

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English
Figure 3-20:      Layer 1 in BGA Area for DACs/ADCs

X-Ref Target - Figure 3-20

X22698-Layer_1_in_BGA_Area_for_DACs_and_ADCs.jpg

Guidance:

Land pads = 20 mils for signal and grounds for BGA balls

Anti-pads for signals = 34 mils

Anti-pads for grounds = 30 mils

Micro via for layer 2 routes = 6 mil drill

Via for layer 4 routes = 8 mil drill (back-drilled)

Add extra horizontal ground vias between ground solder balls at 20 mil pitch (see This Figure)

Ground vias = 8 mil drill

Land pad for extra grounds = 16 mils

Thermal relief for ground pads (5 mil width vertical route and 9 mil width horizontal route)