Layer 3 in BGA Area for DACs/ADCs

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English
Figure 3-22:      Layer 3 in BGA Area for DACs/ADCs

X-Ref Target - Figure 3-22

X22700-Layer_3_in_BGA_Area_for_DACs_and_ADCs.jpg

Guidance:

There should be no anti-pads underneath the micro-vias used for the layer 2 routes.

Remove all unused pads.

Anti-pads for vias should be 35 mils.

Land pad for all grounds should be 18 mils.