Layer 6 for Clock Routes

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English
Figure 3-25:      Layer 6 for Clock Routes

X-Ref Target - Figure 3-25

X22703-Layer_6_for_Clock_Routes.jpg

Guidance:

Trace width of 5.8 mils. Neck down trace of 40 mils to achieve RL of –15 dB @10 GHz is required.

Air gap between traces should be 15 mils.

Signal gap to ground should be 15 mils.

Ground guard trace width should be 18 mils.