Layer Height

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

As the layer height (H) is increased, the impedance increases, while the signal propagation delay remains unchanged, and vice-versa. When reducing or increasing layer height, consider that layer heights that are too low can be more expensive to reliably manufacture, because the PCB fabricator must avoid plane shorts. Layer heights that are too high can lead to aspect ratio violations. The associations in Table: Relationship of Trace Width to Impedance, Required Spacing, and Propagation Delay show the effect of layer height on impedance and propagation delay.

Table 2-7:      Relationship of Layer Height to Impedance and Propagation Delay

­

Z0 ­

TPD (no change)

¯

Z0 ¯

TPD (no change)