Memory Derating Tables

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

The skew numbers presented in PCB Guidelines for Memory Interfaces were calculated to operate the memory interfaces at their maximum data rates. Some of those skew limits can be relaxed if the respective memory interface is not intended to be operated at the maximum data rate. The tables in this appendix represent the extent to which the respective skew numbers can be relaxed based on the speed rating of the FPGA, the memory component rating, and the actual speed at which the system is operated. For example, for DDR3 DQ to DQS (Table: DDR3 Data to DQS Skew Limit) using an FPGA rated at 2133 Mb/s and a memory component rated at 1333 Mb/s while operating at 1333 Mb/s, the skew can be relaxed from 10 ps to 87 ps. The derating tables are valid for both PL and PS memory interfaces.

Note: The shaded numbers in Table: DDR3 Data to DQS Skew Limit to Table: QDR II+ ADDR/CMD to CLK Skew Limit for Clock T-Branch and CA T-Branch represent the maximum skew (plus or minus) allowed for the given FPGA speed rating and memory component rating when operated at that speed.

Table E-1: DDR3 Data to DQS Skew Limit
FPGA Rating (Mb/s)		Memory Component Rating (Mb/s)
Rated	Actual	2133	1866	1600	1333	1066	800
2133	2133	10	N/A	N/A	N/A	N/A	N/A
	1866	39	26	N/A	N/A	N/A	N/A
	1600	83	70	52	N/A	N/A	N/A
	1333	146	133	114	87	N/A	N/A
	1066	150	150	150	150	146	N/A
	800	150	150	150	150	150	150
1866	1866	18	10	N/A	N/A	N/A	N/A
	1600	63	50	31	N/A	N/A	N/A
	1333	125	112	94	66	N/A	N/A
	1066	150	150	150	150	125	N/A
	800	150	150	150	150	150	150
1600	1600	36	23	10	N/A	N/A	N/A
	1333	99	86	68	40	N/A	N/A
	1066	150	150	150	134	99	N/A
	800	150	150	150	150	150	150
1333	1333	64	51	33	10	N/A	N/A
	1066	150	145	126	99	64	N/A
	800	150	150	150	150	150	150
1066	1066	99	86	68	40	10	N/A
1066	800	150	150	150	150	150	99
800	800	150	148	130	102	67	10
Notes: 1.See Table: DDR3 SDRAM Data Group Skew Constraints and Table: DDR3 DIMM Data Group Skew Constraints for the original specifications associated with this table.

Table E-2: DDR3 Address/Command/Control to CK Skew Limit
FPGA Rating (Mb/s)		Memory Component Rating (Mb/s)
Rated	Actual	2133	1866	1600	1333	1066	800
2133	2133	8	N/A	N/A	N/A	N/A	N/A
	1866	8	8	N/A	N/A	N/A	N/A
	1600	32	32	32	N/A	N/A	N/A
	1333	77	77	77	77	N/A	N/A
	1066	119	119	119	119	119	N/A
	800	150	150	150	150	150	150
1866	1866	8	8	N/A	N/A	N/A	N/A
	1600	32	32	32	N/A	N/A	N/A
	1333	77	77	77	77	N/A	N/A
	1066	119	119	119	119	119	N/A
	800	150	150	150	150	150	150
1600	1600	32	28	8	N/A	N/A	N/A
	1333	77	77	77	77	N/A	N/A
	1066	119	119	119	119	119	N/A
	800	150	150	150	150	150	150
1333	1333	58	48	28	8	N/A	N/A
	1066	119	119	119	119	119	N/A
	800	150	150	150	150	150	150
1066	1066	119	119	101	81	8	N/A
1066	800	150	150	150	150	150	150
800	800	150	150	150	150	150	150
Notes: 1.See Table: DDR3 SDRAM Address, Command, and Control Skew Constraints and Table: DDR3 DIMM Address, Command, and Control Skew Constraints for the original specifications associated with this table.

Table E-3: DDR4 Data to DQS Skew Limit
FPGA Rating (Mb/s)	Running At (Mb/s)	Memory Component Rating (Mb/s)
FPGA Rating (Mb/s)	Running At (Mb/s)	3200	2933	2666	2400	2133	1866	1600
2666	2666	18	16	10	N/A	N/A	N/A	N/A
	2400	38	37	31	24	N/A	N/A	N/A
	2133	64	63	57	50	46	N/A	N/A
	1866	98	96	90	83	79	66	N/A
	1600	142	141	135	128	124	110	92
2400	2400	25	23	17	10	N/A	N/A	N/A
	2133	51	49	43	36	32	N/A	N/A
	1866	84	82	77	70	65	52	N/A
	1600	129	127	121	114	110	97	79
2133	2133	29	27	21	14	10	N/A	N/A
	1866	62	61	55	48	44	30	N/A
	1600	107	105	99	92	88	75	57
1866	1866	42	40	35	28	23	10	N/A
1866	1600	87	85	79	72	68	55	37
1600	1600	60	58	52	45	41	28	10
Notes: 1.See Table: DDR4 SDRAM Data Group Skew Constraints and Table: DDR4 DIMM Skew Constraints for the original specifications associated with this table.

Table E-4: DDR4 Address/Command/Control to CK Skew Limit
FPGA Rating (Mb/s)	Running At (Mb/s)	Memory Component Rating (Mb/s)
FPGA Rating (Mb/s)	Running At (Mb/s)	3200	2933	2666	2400	2133	1866	1600
2666	2666	23	15	8	N/A	N/A	N/A	N/A
	2400	65	57	50	43	N/A	N/A	N/A
	2133	117	109	102	95	77	N/A	N/A
	1866	150	150	150	150	144	124	N/A
	1600	150	150	150	150	150	150	150
2400	2400	30	22	15	8	N/A	N/A	N/A
	2133	82	74	67	60	42	N/A	N/A
	1866	149	141	134	127	109	89	N/A
	1600	150	150	150	150	150	150	150
2133	2133	48	40	33	26	8	N/A	N/A
	1866	115	107	100	93	75	55	N/A
	1600	150	150	150	150	150	144	129
1866	1866	68	60	53	46	28	8	N/A
1866	1600	150	149	142	135	117	97	82
1600	1600	83	75	68	61	43	23	8
Notes: 1.See Table: DDR4 SDRAM Address, Command, and Control Skew Constraints and Table: DDR4 DIMM Address, Command, and Control Skew Constraints for the original specifications associated with this table.

Table E-5: RLDRAM 3 DQ/DM to DK_P/N Skew Limit
FPGA Rating (MHz)		Memory Component Rating (MHz)
Rated	Running at	1200	1066	933	800
1200	1200	5	N/A	N/A	N/A
	1066	31	26	N/A	N/A
	933	65	60	45	N/A
	800	109	104	89	64
1066	1066	10	5	N/A	N/A
	933	43	38	23	N/A
	800	88	83	68	43
933	933	25	20	5	N/A
933	800	70	65	50	25
800	800	50	45	30	5
Notes: 1.See Table: RLDRAM 3 Memory Skew Constraints for the original specifications associated with this table.

Table E-6: RLDRAM 3 DQ to QK_P/N Skew Limit
FPGA Rating (MHz)		Memory Component Rating (MHz)
Rated	Running at	1200	1066	933	800
1200	1200	5	N/A	N/A	N/A
	1066	31	6	N/A	N/A
	933	65	40	9	N/A
	800	109	84	54	13
1066	1066	30	5	N/A	N/A
	933	63	38	8	N/A
	800	108	83	53	11
933	933	60	35	5	N/A
933	800	105	80	50	8
800	800	105	77	46	5
Notes: 1.See Table: RLDRAM 3 Memory Skew Constraints for the original specifications associated with this table.

Table E-7: RLDRAM 3 DK_P/N to CK_P/N Skew Limit
FPGA Rating (MHz)		Memory Component Rating (MHz)
Rated	Running at	1200	1066	933	800
1200	1200	5	N/A	N/A	N/A
	1066	57	29	N/A	N/A
	933	124	96	60	N/A
	800	150	150	149	101
1066	1066	33	5	N/A	N/A
	933	100	72	36	N/A
	800	150	150	125	77
933	933	69	41	5	N/A
933	800	150	130	94	46
800	800	118	89	53	5
Notes: 1.See Table: RLDRAM 3 Memory Skew Constraints for the original specifications associated with this table.

Table E-8: RLDRAM 3 ADDR/CMD to CK_P/N Skew Limit
FPGA Rating (MHz)		Memory Component Rating (MHz)
Rated	Running at	1200	1066	933	800
1200	1200	5	N/A	N/A	N/A
	1066	57	42	N/A	N/A
	933	124	109	74	N/A
	800	150	150	150	128
1066	1066	20	5	N/A	N/A
	933	87	72	37	N/A
	800	150	150	126	91
933	933	55	40	5	N/A
933	800	144	129	94	59
800	800	90	75	40	5
Notes: 1.See Table: QDR II+ SRAM Skew Constraints for the original specifications associated with this table.

Table E-9: QDR II+ D to K_P/N Skew Limit
FPGA Rating (MHz)		Memory Component Rating (MHz)
Rated	Actual	633	600	550
633	633	6	N/A	N/A
	600	27.72	27.72	N/A
	550	65.6	65.6	65.6
600	633	N/A	N/A	N/A
	600	6	6	N/A
	550	43.88	43.88	43.88
550	633	N/A	N/A	N/A
	600	N/A	N/A	N/A
	550	6	6	6
Notes: 1.See Table: QDR II+ SRAM Skew Constraints for the original specifications associated with this table.

Table E-10: QDR II+ Q to CQ_P/N Skew Limit
FPGA Rating (MHz)		Memory Component Rating (MHz)
Rated	Actual	633	600	550
633	633	6	N/A	N/A
	600	27.72	27.72	N/A
	550	65.6	65.6	6
600	633	N/A	N/A	N/A
	600	6	6	N/A
	550	43.88	43.88	6
550	633	N/A	N/A	N/A
	600	N/A	N/A	N/A
	550	66	66	6
Notes: 1.See Table: QDR II+ SRAM Skew Constraints for the original specifications associated with this table.

Table E-11: QDR II+ Data Skew Limit
FPGA Rating (MHz)		Memory Component Rating (MHz)
Rated	Actual	633	600	550
633	633	5	N/A	N/A
	600	42.88	42.88	N/A
	550	64.6	64.6	64.6
600	633	N/A	N/A	N/A
	600	5	5	N/A
	550	42.88	42.88	42.88
550	633	N/A	N/A	N/A
	600	N/A	N/A	N/A
	550	5	5	5
Notes: 1.See Table: QDR II+ SRAM Skew Constraints for the original specifications associated with this table.

Table E-12: QDR II+ ADDR/CMD Skew Limit
FPGA Rating (MHz)		Memory Component Rating (MHz)
Rated	Actual	633	600	550
633	633	6	N/A	N/A
	600	49.44	49.44	N/A
	550	125.2	125.2	125.2
600	633	N/A	N/A	N/A
	600	6	6	N/A
	550	81.76	81.76	81.76
550	633	N/A	N/A	N/A
	600	N/A	N/A	N/A
	550	6	6	6
Notes: 1.See Table: QDR II+ SRAM Skew Constraints for the original specifications associated with this table.

Table E-13: QDR II+ ADDR/CMD to CLK Skew Limit for Clock Point-to-Point and CA Fly-by
FPGA Rating (MHz)		Memory Component Rating (MHz)
Rated	Actual	633	600	550
633	633	6	N/A	N/A
	600	49.44	49.44	N/A
	550	125.2	125.2	125.2
600	633	N/A	N/A	N/A
	600	6	6	N/A
	550	81.76	81.76	81.76
550	633	N/A	N/A	N/A
	600	N/A	N/A	N/A
	550	6	6	6
Notes: 1.See Table: QDR II+ SRAM Skew Constraints for the original specifications associated with this table.

Table E-14: QDR II+ ADDR/CMD to CLK Skew Limit for Clock T-Branch and CA Fly-by
FPGA Rating (MHz)		Memory Component Rating (MHz)
Rated	Actual	633	600	550
633	633	34	N/A	N/A
	600	77.44	77.44	N/A
	550	153.2	153.2	153.2
600	633	N/A	N/A	N/A
	600	34	34	N/A
	550	109.76	109.76	109.76
550	633	N/A	N/A	N/A
	600	N/A	N/A	N/A
	550	34	34	34
Notes: 1.See Table: QDR II+ SRAM Skew Constraints for the original specifications associated with this table.

Table E-15: QDR II+ ADDR/CMD to CLK Skew Limit for Clock T-Branch and CA T-Branch
FPGA Rating (MHz)		Memory Component Rating (MHz)
Rated	Actual	633	600	550
633	633	6	N/A	N/A
	600	49.44	49.44	N/A
	550	125.2	125.2	125.2
600	633	N/A	N/A	N/A
	600	6	6	N/A
	550	81.76	81.76	81.76
550	633	N/A	N/A	N/A
	600	N/A	N/A	N/A
	550	6	6	6
Notes: 1.See Table: QDR II+ SRAM Skew Constraints for the original specifications associated with this table.