The total P to N skew should be no longer than 2000 fs (2.0 ps). This skew specification is broken down into two components:
•±1000 fs (1.0 ps) using simulation and taking into account RFSoC package delays and PCB trace length mismatch.
•±1000 fs (1.0 ps) due to manufacturing variations.
Simulations should include a complete channel s-parameter analysis that includes the RFSoC package and PCB S-parameter models. The PCB should be deskewed using the simulation analysis to meet the 1000 fs specification. You can request the package S-parameter models for the ADC/DAC channels by talking to your I/O/RF specialist.
Manufacturing variations can be minimized via the following methods:
•1086 Mechanically Spread (MS) Glass, 700–900 fs skew per inch: MS glass is spread in both directions to achieve greater homogeneity.
•NE glass, 400–600 fs per inch: Replacing E-glass with NE glass can provide for further skew reduction.
•Image Rotation, 500–100 fs skew per inch: Rotating the image on the PCB panel, as shown in This Figure, can help offset panel x-y non-homogeneity. The recommended rotation is 12 degrees.
•Trace Length Matching, ~150 fs: Matching the P and N trace length to 1 mil (0.0254 mm) can help to achieve approximately 150 fs of skew. Trace length matching should be done as close as possible to any AC coupling capacitors. See Table: Trace Length Matching for suggested specifications.
|
Component |
Type of Skew |
Specification (mil) |
Comments |
|---|---|---|---|
|
DAC/ADC data converters |
Intra Pair |
±1 |
Imbalance here impacts the data converter HD2. Can be relaxed to ±5 if not important on application. |
|
ADC clock |
Intra Pair |
±5 |
|
|
DAC clock |
Intra Pair |
±5 (or ±2(1)) |
|
|
DAC data converters |
Inter Pair |
±10 |
Matching only required if required by application. |
|
ADC data converters |
Inter Pair |
±10 |
Matching only required if required by application. No matching required between DACs and ADCs. |
|
ADC clocks(2) |
Inter Pair |
±10 |
Clock matching is only required when using the MTS feature. |
|
DAC clocks(3) |
Inter Pair |
±10 |
Don't need to match to ADC clocks. |
|
Notes: 1.A tighter P to N skew is required on the DAC clock if using an external RF sampling clock. This is not required if using internal PLL. 2.Applied only when MTS is required for ADC group and sample clock feeds directly to tiles. 3.Applied only when MTS is required for DAC group and sample clock feeds directly to tiles. |
|||
When routing a 180-degree bend of a P/N pair, the minimum bend radius must be 3H. This distance allows for a guard trace and ground stitching vias to be placed between the two segments of the inner trace, before and after the bend. Ground stitching vias must be placed on the guard trace in this inner region with the final ground via placed at the end of the guard trace near the signal trace bend. This Figure shows a properly routed P/N trace pair 180-degree bend with guard trace and ground stitching vias.
If routing below 1 mm radius is required in tight areas, calculate the electrical length by following the path of the inner radius of the arc. Most EDA tools calculate the delay based on the center line radius of the arc segment. For example, for a 4 mil wide trace with an arc segment with a 10 mil center line radius, the signal actually follows the radius of
10 – (4/2) = 8 mil. The effect of the signal following the inner radius of the arc begins at roughly 10 MHz and remains constant enough that no further optimization is needed for higher frequencies up to 10 GHz.
When P/N traces transition layers, two ground vias must be added per signal for impedance control, noise isolation, and P/N skew control. The ground vias must be within 1 mm of the signal vias. This Figure illustrates the via configuration for a signal layer transition.
P/N signal traces should be routed a minimum of 0.5H away from any anti-pad or cutout in the ground planes above or below the signal traces. The left side of This Figure illustrates an incorrectly routed signal trace. The right side of This Figure illustrates the correct routing of a signal trace.
Signal guard traces must be continuous with no breaks and must have proper ground stitching. An improperly implemented guard trace could result in additional P/N skew as well as increased noise susceptibility.