Table: PCB Design Checklist for PS-GTR is a checklist of items that can be used to design and review any Zynq UltraScale+ MPSoC PS-GTR transceiver schematic and layout.
|
Pins |
Recommendations |
|---|---|
|
PS_MGTREFCLK0P PS_MGTREFCLK0N PS_MGTREFCLK1P PS_MGTREFCLK1N PS_MGTREFCLK2P PS_MGTREFCLK2N PS_MGTREFCLK3P PS_MGTREFCLK3N |
•Use AC coupling capacitors for connection to oscillator. •For AC coupling capacitors, see Reference Clock Interface. The recommended value for LVDS is 10 nF. •Reference clock traces should be provided enough clearance to eliminate crosstalk from adjacent signals. •Reference clock oscillator output must comply with the minimum/maximum input amplitude requirements for these input pins. See the PS-GTR Transceiver Clock DC Input Level Specifications table in Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 22]. •PS-GTR reference clock PS_MGTREFCLKxP/N should be stable before releasing PS_POR_B. •If the reference clock input is not used, leave the associated pin pair unconnected or tie to ground. •Traces should be routed to 50W single-ended/100W differential. |
|
PS_MGTRRXP0/ PS_MGTRRXN0 PS_MGTRRXP1/ PS_MGTRRXN1 PS_MGTRRXP2/ PS_MGTRRXN2 PS_MGTRRXP3/ PS_MGTRRXN3 |
•Use AC coupling capacitors for connection to the transmitter. The recommended value for AC coupling capacitors is 100 nF (176 nf to 265 nf for PCI Express®). •Receiver data traces should be provided enough clearance to eliminate crosstalk from adjacent signals. •If a receiver is not used, leave the associated pin pair unconnected or tie to ground. •Trace match P/N to 10% (or less) of the UI. •Traces should be routed to 50W single-ended/100W differential(1). |
|
PS_MGTRTXP0/ PS_MGTRTXN0 PS_MGTRTXP1/ PS_MGTRTXN1 PS_MGTRTXP2/ PS_MGTRTXN2 PS_MGTRTXP3/ PS_MGTRTXN3 |
•The transmitter should be AC coupled to the receiver. The recommended value for the AC coupling capacitors is 100 nF (176 nf to 265 nf for PCI Express®). •Transmitter data traces should be provided enough clearance to eliminate crosstalk from adjacent signals. •If a transmitter is not used, leave the associated pin pair unconnected or tie to ground. •Trace match P/N to 10% (or less) of the UI. •Traces should be routed to 50W single-ended/100W differential(1). |
|
PS_MGTRREF |
•Connect to a 500W 0.5% resistor to this pin with the other terminal of the resistor connected to ground. •Can be left unconnected or tied to ground if the transceivers will not be used. |
|
PS_MGTRAVCC |
•The nominal voltage is 0.85 VDC. •See the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 22] for power supply voltage tolerances. •Not sharing this supply with other non-transceiver loads reduces the chance of exceeding the noise requirement for the power supply. •The following filter is recommended: °One of 10 µF 10% ceramic •For optimal performance, power supply noise must be less than 10 mVPP. If the noise on the power supply is less than or equal to this requirement, the performance of the transceiver will not be negatively impacted. •If all of the PS-GTR transceivers in the Quad are not used, the associated power pins can be left unconnected or tied to ground. •For power consumption, refer to the Xilinx Power Estimator (XPE). |
|
PS_MGTRAVTT |
•The nominal voltage is 1.8 VDC. •See Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 22] for power supply voltage tolerances. •Not sharing this supply with other non-transceiver loads reduces the chance of exceeding the noise requirement for the power supply. •The following filter is recommended: °One of 10 µF 10% ceramic •If all of the PS-GTR transceivers in the Quad are not used, the associated power pins can be left unconnected or tied to ground. •For power consumption, refer to the Zynq UltraScale+ MPSoC XPower Estimator at Xilinx Power Estimator (XPE). |
|
Notes: 1.The USB 3.0/SuperSpeed specification calls for differential trace routing of 90W ±15W. |
|