PCB Routing Guidelines for LPDDR4 Memories in High-Density Interconnect Boards

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

The LPDDR4 routing guidelines for AMD devices that are placed on high-density interconnect (HDI) boards are different from those for standard printed circuit board technologies. The recommended routing of LPDDR4 signals between the FPGA and DRAM device is shown in This Figure, with a reference PCB shown in This Figure. Routing begins from the BGA ball with a short stub to a blind via (top layer to inner layer) which travels to layer three. The routing from the BGA ball to where it is no longer under the BGA is referred to as the breakout area and can typically be the most difficult area to route due to tight spacing of pins and vias. After traveling outside of the breakout area into the main routing area, the signal then travels under the DRAM breakout area, through a blind via, to the DRAM pin. This Figure also shows how blind and buried vias (vias between inner layers) can be used in cases where spacing is too tight for just one blind via.

Figure 2-51: Examples of Stripline Routing for HDI LPDDR4 Signals
X-Ref Target - Figure 2-51

Figure 2-52: Reference PCB with Routing Areas Denoted
X-Ref Target - Figure 2-52

Refer to Table: Routing Guidelines for HDI LPDDR4 Signals for the physical and timing rules.

Table 2-60: Routing Guidelines for HDI LPDDR4 Signals
Parameter	Value	Notes
Bitrate	1066 Mb/s
PCB thickness	37 mil ± 10%	Typical board thickness for HDI. Assumes FPGA and memory component on same side of PCB.
FPGA/DRAM component placement	Top layer
Number of routing layers to route LPDDR4 signals	3 (for FGAA530 package)	Top, Layer 3, Layer 5
Maximum distance between FPGA ball and blind via	70 mil
Maximum distance between DRAM ball and blind via	300 mil
Maximum distance between FPGA ball and DRAM ball	2000 mil
Via type	Blind	Maximum 4 (see next row)
Blind/buried via routing (see This Figure)	Top-L3-Top	2 Vias
	Top-L5-Top	2 Vias
	Top-L3-L5-L3-Top	4 Vias
Maximum skew: P/N	±2 ps	DQS, CK signals
Maximum skew: DQ to DQS	±5 ps
Maximum skew: CAC to CK	±8 ps
Trace Impedance (single-ended)	50W ± 10%
Trace Impedance (differential)	100W ± 10%
Minimum spacing: CAC Signals	2.5 ´ H⁽¹⁾	Within same channel
Minimum spacing: CAC Signals to CK	4.5 ´ H⁽¹⁾	Within same channel
Minimum spacing: CAC/CK to DQ/DQS	7.5 ´ H⁽¹⁾	Within same channel
Minimum spacing: DQ Signals	2.5 ´ H⁽¹⁾	Within same byte (main)
Minimum spacing: DQ to DQS	2.5 ´ H⁽¹⁾	Within same byte (main)
Minimum spacing: DQ/DQS Signals	4.5 ´ H⁽¹⁾	To different bytes
Minimum spacing: DQ/DQS Signals	4.5 ´ H⁽¹⁾	To other signals in the same channel
Minimum spacing	7.5 ´ H⁽¹⁾	To signals in different channels or interfaces
Notes: 1.H is the distance between the routing layer and closest reference plane.