PCB Routing Guidelines for MIPI D-PHY

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

MIPI D-PHY is intended for use in mobile devices including cameras, displays, and unified protocol interfaces. This standard is only supported in the HP I/O banks of the Kintex UltraScale+ and Virtex UltraScale+ FPGAs, and Zynq UltraScale+ MPSoCs. Support for this standard in UltraScale devices is in adherence to the MIPI alliance interface specifications. Typical MIPI D-PHY cores consist of four differential data lanes and one differential clock lane, as shown in This Figure.

Figure 5-1: MIPI D-PHY Transmitter and Receiver Paths
X-Ref Target - Figure 5-1

MIPI D-PHY PCB guidelines for impedance, trace length, spacing, skew, and termination are shown in Table: MIPI D-PHY PCB Trace and Skew Guidelines.

Table 5-1: MIPI D-PHY PCB Trace and Skew Guidelines
Parameter	Specification
Trace type	Stripline
Differential impedance	95±10% W
Trace length	£ 10.0 inches⁽¹⁾⁽²⁾
Spacing in pair	2X trace width
Spacing to other MIPI pairs	5X trace width
Spacing to other non-MIPI pairs	6X trace width
Skew between P/N per pair	±2 ps
Skew between clock and data	±8 ps
Skew between data and data	±8 ps
Termination at receiver	100W differential⁽³⁾
Notes: 1.For distances greater than 4 inches, receiver equalization must be used (CTLE). It is strongly recommended that the PCB (data-to-data and data-to-clock) be deskewed even if the deskew feature in the IP is used. 2.A reference stackup used for the longer trace lengths (4 to 10 inches) can be provided upon request. Operation at 2.5 Gb/s is supported as long as the channel loss is kept under 9 dB. 3.When FPGA/MPSoC is the receiver, 100W on-chip termination is recommended via the DIFF_TERM attribute. See the MIPI_DPHY section in UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 10].