PCB Stackup and Layer Order

V_CC and ground plane placement in the PCB stackup (the layer order) has a significant impact on the parasitic inductances of power current paths. Layer order must be considered early in the design process:

•High-priority supplies should be placed closer to the FPGA (in the PCB stackup’s top half)

•Low-priority supplies should be placed farther from the FPGA (in the PCB stackup’s bottom half)

Power supplies with high transient current should have the associated V_CC planes close to the top surface (FPGA side) of the PCB stackup. This decreases the vertical distance (V_CC and GND via length) that currents travel before reaching the associated V_CC and GND planes. To reduce spreading inductance, every V_CC plane should have an adjacent GND plane in the PCB stackup. The skin effect causes high-frequency currents to couple tightly, and the GND plane adjacent to a specific V_CC plane tends to carry the majority of the current complementary to that in the V_CC plane. Thus, adjacent V_CC and GND planes are treated as a pair.

Not all V_CC and GND plane pairs reside in the PCB stackup’s top half because manufacturing constraints typically require a symmetrical PCB stackup around the center (with respect to dielectric thicknesses and etched copper areas). The PCB designer chooses the priority of the V_CC and GND plane pairs: high priority pairs carry high transient currents and are placed high in the stackup, while low priority pairs carry lower transient currents (or can tolerate more noise) and are placed in the lower part of the stackup.