Propagation delay for a given net across two devices in a footprint compatible package are not identical. Skews within a data group are controlled, however, such that the maximum skew in a data bye is ±30 ps. This Figure illustrates these potential differences. For migration purposes, a one speed grade performance hit should be assumed by default to account for this additional skew. See Table: DDR4 SDRAM Performance in UltraScale+ FPGAs in the Presence of Migration for Single-Rank Component for an example of speed grade performance impact.
