Pi Network for Improved Return Loss in Gen 1 Devices (XCZU25DR/XCZU27DR/XCZU28DR/XCZU29DR)

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

AMD ADCs and DACs have a nominal on-die 100W differential termination, which generally provides sufficient return loss performance for most RF applications. However, for applications requiring better that –10 dB return loss up to 4 GHz, AMD recommends placing –2 dB balanced Pi pad attenuators on the PCB. These Pi pad attenuators can be placed anywhere on the PCB between the ADC/DAC BGA balls of the package and the baluns. A representative –2 dB Pi pad attenuator for a differential ADC/DAC is shown in This Figure.

Figure 3-16:      –2 dB Pi Attenuation Network (XCZU25DR/XCZU27DR/XCZU28DR/XCZU29DR)

X-Ref Target - Figure 3-16

X19905--2-db-pi-attenuation-network.jpg

The component descriptions are listed below with recommended part numbers:

R2 = R3 = 11.5W (Panasonic part number ERJ-1GEF11R5C)

R1 = R4 = 866W (Panasonic part number ERJ-1GEF8660C)

AMD recommends the following characteristics for the discrete resistive components:

0201 body size or smaller to minimize parasitic inductance.

±1% resistor tolerance or better to minimize insertion loss variation

100 ppm/°C temperature coefficient or better to minimize variation of the resistance value over temperature

For purposes of PCB routing, there should be a minimum of four ground vias for each and every signal via. The length of the vias and trace routing between components should be minimized as much as possible. Placing the Pi pad attenuators underneath cans minimizes crosstalk between them.

 

IMPORTANT:   For all generations of RFSoC later than Gen 1, there is no need for an attenuator due to improvements in return loss performance of both DAC and ADC.