Pin Description and Design Guidelines

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

Table: PS-GTR Transceiver Quad Pin Descriptions and This Figure detail the PCB guidelines for PS-GTR transceiver interfaces.

Table 4-1:      PS-GTR Transceiver Quad Pin Descriptions

Pins

Direction

Descriptions

PS_MGTREFCLK[3:0]P
PS_MGTREFCLK[3:0]N

In (Pad)

Differential clock input pin pair for the reference clock of the PS-GTR transceiver.

PS_MGTRRXP[3:0] PS_MGTRRXN[3:0]

In (Pad)

RXP and RXN are the differential input pairs for each of the PS-GTR receivers.

PS_MGTRTXP[3:0] PS_MGTRTXN[3:0]

Out (Pad)

TXP and TXN are the differential output pairs for each of the PS-GTR transmitters.

PS_MGTRREF

In (Pad)

Calibration input pin for the termination resistor calibration circuit.

PS_MGTRAVCC

In (Pad)

MGTRAVCC is the receiver, transmitter, and clock core power supply. The nominal voltage 0.85 VDC.

PS_MGTRAVTT

In (Pad)

MGTRAVTT is the I/O supply for the transmitter and receiver. The nominal voltage is 1.8 VDC.

Figure 4-1:      PS-GTR External Power Supply and Calibration Resistor Connections

X-Ref Target - Figure 4-1

ug583_c8_18.jpg

Note relevant to This Figure:

The voltage values are nominal. See the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 22] for values and tolerances.