Sometimes the decoupling network capacitance is adequate, but there is too much inductance in the path from the capacitors to the FPGA.
Possible causes are:
•Wrong decoupling capacitor connecting-trace geometry or solder-land geometry
•The path from the capacitors to the FPGA is too long
- and/or -
•A current path in the power vias traverses an exceptionally thick PCB stackup
For inadequate connecting trace geometry and capacitor land geometry, review the loop inductance of the current path. If the vias for a decoupling capacitor are spaced a few millimeters from the capacitor solder lands on the board, the current loop area is greater than necessary.
To reduce the current loop area, vias should be placed directly against capacitor solder lands. Never connect vias to the lands with a section of trace.
Other improvements of geometry are via-in-pad (via under the solder land), not shown, and via-beside-pad (vias straddle the lands instead of being placed at the ends of the lands). Double vias also improve connecting trace geometry and capacitor land geometry.
Exceptionally thick boards (> 3.2 mm or 127 mils) have vias with higher parasitic inductance.
To reduce the parasitic inductance, move critical VCC/GND plane sandwiches close to the top surface where the FPGA is located, and place the capacitors on the top surface where the FPGA is located.