Possibility 3: I/O Signals in PCB are Stronger Than Necessary

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

If noise in the VCCO PDS is still too high after refining the PDS, the I/O interface slew rate and/or drive strength can be reduced. This applies to both outputs from the FPGA and inputs to the FPGA. In severe cases, excessive overshoot on inputs to the FPGA can reverse-bias the IOB clamp diodes, injecting current into the VCCO PDS.

If large amounts of noise are present on VCCO , the drive strength of these interfaces should be decreased, or different termination should be used (on input or output paths).