Power Delivery Network Design for Time Division Duplex

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

For details on the time division duplex (TDD) feature, refer to Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269) [Ref 17]. Usage of the TDD mode requires a power distribution network (PDN) on the PCB with very fast step response settling times. The TDD feature puts some of the RFDC IP data converter supplies in a low-power state when in non-active mode, and switches back to full-power mode while in active mode in under 1 µs. The PDN needs to be able to respond to this step response with a similar settling time to maximize the power saving offered by the TDD mode. Customers can use the Xilinx Power Estimator (XPE) tool to calculate the step change in current by using the duty cycle set at 100% and 0% to get the full power and low power currents. A typical fast settling reference design can be found on the ZCU208 or ZCU216 evaluation boards. TDD power saving mode is only supported in Gen 3 and DFE devices. The glitches in the PDN introduced by the TDD switching should be kept within the tolerance of the ±3% of the supplies.