Zynq UltraScale+ MPSoCs contain a number of power rails that correspond to the variety of features contained within the devices. A complete list of the power rails for Zynq UltraScale+ MPSoCs is listed in Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 22].
For most purposes, assuming the decoupling requirements and filtering requirements are met, many of the power rails can be consolidated to reduce the total number of power regulators required to power a Zynq UltraScale+ MPSoC. In many applications, only five power regulators are required to power a Zynq UltraScale+ MPSoC. (Some of the five power regulators might be shared with other devices in the system.) However, the amount of consolidation that is possible depends on user requirements.
For example, many applications periodically need to enter ultra-low power, reduced functionality states to extend battery life or to reduce their overall power consumption. To facilitate this, Zynq UltraScale+ MPSoCs have four independent power domains that can be individually isolated: low-power domain (LPD), full-power domain (FPD), PL power domain (PLPD), and battery power domain (BPD). Applications requiring access to these ultra-low power states that cannot be achieved via power gating options in software might need independent control of the power rails associated with each power domain to enable the power associated with unused domains to reduce to zero. This results in the need for more power regulators or for the use of load switches. In this document, this use case is referred to as full power management flexibility. More detail on Zynq UltraScale+ MPSoC power domains can be found in Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 23] and Managing Power and Performance with the Zynq UltraScale+ MPSoC (WP482) [Ref 24]. The benefits of leveraging the power domains and having full power management flexibility can be quantified using the Xilinx Power Estimator (XPE) tool.
Other applications nearly always operate at full performance or can meet their power targets by disabling functionality via IP power-gating options (e.g., disabling processor cores or clock gating portions of the programmable logic). These applications do not need individual control of the power rails associated with each power domain. Therefore, these applications can achieve the maximum amount of power supply consolidation. For simplicity in this user guide, these applications are referred to as always on, and are further classified into three unique use cases. Together with the first use case (full power management flexibility), a total of four key use cases are discussed in this section:
•Always on: Cost optimized (-1 and -2 devices)
•Always on: Power/efficiency optimized (-1L and -2L devices)
•Always on: PL performance optimized (-3 devices)
•Full power management flexibility (all devices/speed grades)
The remainder of this section illustrates the power supply consolidation that can be achieved for the above use cases. In addition, Power Management Partners provides links to power delivery solutions from a range of AMD power delivery partners for the use cases mentioned above.