It is preferred to have dedicated K and K_B for each SRAM, but if that is not possible, the T-branch topology is an option. This Figure and Table: Impedance, Length, and Spacing Guidelines for Clock Signals define the topology and routing guidelines for QDR II+ SRAM clock signals.
|
Parameter |
L0 |
L1 |
L2 |
Units |
---|---|---|---|---|
Trace type |
Stripline |
Stripline |
Microstrip |
– |
Single-ended impedance Z0 |
50±10% |
39±10% |
60±10% |
W |
Routing layers |
Upper/Lower |
Upper/Lower |
Upper/Lower |
|
Trace width |
4.0 |
6.0 |
4.0 |
mil |
Trace length |
0.0~0.8/1.2(1) |
<4.0 |
<0.7 |
inches |
Spacing in byte (minimum) |
4.0 |
12.0 |
4.0 |
mil |
Spacing to other group signals (minimum) |
8.0 |
30 |
30 |
mil |
Maximum PCB via count |
2 |
– |
||
Notes: 1.See item 2 in General Memory Routing Guidelines. |