QDR II+ SRAM Clock (K, K_B, and BWS) T-Branch Routing and Termination

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

It is preferred to have dedicated K and K_B for each SRAM, but if that is not possible, the T-branch topology is an option. This Figure and Table: Impedance, Length, and Spacing Guidelines for Clock Signals define the topology and routing guidelines for QDR II+ SRAM clock signals.

Figure 2-74:      Clock (K, K_B) and BWS T-Branch Routing and Termination for QDR II+ SRAM

X-Ref Target - Figure 2-74

ug583_c2_49.jpg
Table 2-84:      Impedance, Length, and Spacing Guidelines for Clock Signals

Parameter

L0
(Device Breakout)

L1
(Main PCB)

L2
(DRAM Breakout)

Units

Trace type

Stripline

Stripline

Microstrip

Single-ended impedance Z0

50±10%

39±10%

60±10%

W

Routing layers

Upper/Lower

Upper/Lower

Upper/Lower

 

Trace width

4.0

6.0

4.0

mil

Trace length

0.0~0.8/1.2(1)

<4.0

<0.7

inches

Spacing in byte (minimum)

4.0

12.0

4.0

mil

Spacing to other group signals (minimum)

8.0

30

30

mil

Maximum PCB via count

2

Notes:

1.See item 2 in General Memory Routing Guidelines.