QDR II+ SRAM Clock and Data Signals (q/cq/cq

QDR II+ SRAM Clock and Data Signals (q/cq/cq_b) Point-to-Point Routing

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

This Figure shows the QDR II+ SRAM clock and data signals point-to-point routing.

Figure 2-76: Clock and Data Signals (q/cq/cq_b) Point-to-Point Routing
X-Ref Target - Figure 2-76

Table: QDR II+ SRAM Impedance, Length, and Spacing Guidelines for Clock and Data Signals shows the QDR II+ SRAM impedance, length, and spacing guidelines for clock and data signals.

Table 2-85: QDR II+ SRAM Impedance, Length, and Spacing Guidelines for Clock and Data Signals
Parameter	L0 (Device Breakout)	L1 (Main PCB)	L2 (SRAM Breakout)	Units
Trace type	Stripline	Stripline	Stripline	–
d and q single-ended impedance Z₀	50±10%	39±10%	50±10%	W
Trace width (nominal)	4.0	6.0	4.0	mil
Trace length (nominal)	0.0~0.8/1.2⁽¹⁾	0.0~4.0	0.0~0.5	inches
Spacing in byte (minimum)	4.0	8.0	4.0	mil
Spacing byte to byte (minimum)	4.0	20	4.0	mil
CQ_P/N to other spacing	4.0	12.0	4.0	mil
K_P/N to other spacing	4.0	12.0	4.0	mil
Spacing to other group signals (minimum)	8.0	30	30	mil
Maximum PCB via count	2			–
Notes: 1.See item 2 in General Memory Routing Guidelines.