The QDR II+ SRAM interface consists of clock, control, address, command, and data signals as shown in Table: QDR II+ SRAM Interface Signal Description.
Table 2-81: QDR II+ SRAM Interface Signal Description
|
Signal Name
|
Description
|
|
Clock Signals
|
|
k/k_b[1:0]
|
Write data/address/command clock
|
|
cq/cq_b[1:0]
|
Read data clock
|
|
Control Signals
|
|
zq
|
Output impedance match. (Do not make a NC or connect to GND.)
|
|
odt
|
On-die termination select
|
|
Address Signals
|
|
a[19:0]
|
Memory address bus
|
|
Command Signals
|
|
wps_n
|
Write port select
|
|
rps_n
|
Read port select
|
|
Data Signals
|
|
d[35:0]
|
Data input bus
|
|
bws[3:0]
|
Byte write select
|
|
q[35:0]
|
Data output bus
|
|
Other Signals
|
|
VRP
|
240W to GND
|
|
Notes:
1.Actual signal list might vary based on configuration.
|