QDR II+ SRAM Routing Constraints

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

There are two constraints requirements for each signal group in the QDR II+ SRAM interface:

•Maximum length/delay constraints

•Skew constraints

The maximum length/delay constraints are shown in Table: QDR II+ SRAM Maximum Length/Delay Constraints.

Table 2-86: QDR II+ SRAM Maximum Length/Delay Constraints
Signal Group	Reference Figure	Maximum Length/Delay Constraints
address/command	This Figure	6.0 inches 1017 ps
Data signals P0+L0+L1+L2	This Figure	6.0 inches 1017 ps

IMPORTANT: Address and data signals must match lengths to each respective QDR II+ SRAM device.

The skew constraints are listed in Table: QDR II+ SRAM Skew Constraints.

Table 2-87: QDR II+ SRAM Skew Constraints
Signal Group	Skew Constraints (ps)	Skew Constraints (mil)
Data to clock (d to k, q to cq)	±6	±35
Data	±5	±29
T legs	±2	±12
CMD/ADDR (CA)	±6	±35
CMD/ADDR to CLK (CLK point-to-point and CA fly-by	±6	±35
CMD/ADDR to CLK (CLK t-branch and CA fly-by)	±34	±200
CMD/ADDR to CLK (CLK t-branch and CA t-branch)	±6	±35
k to k_b	2	12
q to q_b	2	12
Notes: 1.For skew specifications, refer to the General Memory Routing Guidelines items 3–8.

IMPORTANT: FPGA package flight times must be included in both total length constraints and skew constraints. When minimum and maximum values are available for the package delay, use the midrange between the minimum and maximum values. Memory device package flight times do not need to be factored in because their variances have been accounted for in these guidelines.