This Figure and Table: Address and Command T-Branch Routing and Termination for QDR II+ SRAM show the QDR II+ SRAM address and command T-branch routing, termination topology, and routing guidelines.
|
|
Parameter |
L0 |
L1 (Main PCB) |
L2 (DRAM Breakout) |
L3 (DRAM to DRAM) |
L4 (to RTT) |
Units |
|---|---|---|---|---|---|---|
|
Trace type |
Stripline |
Stripline |
Microstrip |
Microstrip |
Stripline |
– |
|
Single-ended impedance Z0 |
50±10% |
39±10% |
60±10% |
60±10% |
39±10% |
W |
|
Routing layer |
Upper/ |
Upper/ |
Surface |
Surface |
Upper/ |
|
|
Trace width |
4.0 |
6.0 |
4.0 |
4.0 |
6.0 |
mil |
|
Trace length |
0.0~0.8/1.2(1) |
<3.0 |
<0.4 |
<0.7 |
<0.5 |
inches |
|
Spacing in address, command, control signals (minimum) |
4.0 |
12.0 |
4.0 |
8.0 |
8.0 |
mil |
|
Spacing to clock signals (minimum) |
8.0 |
12.0 |
8.0 |
12.0 |
12.0 |
mil |
|
Spacing to other group signals (minimum) |
8.0 |
30 |
30 |
30 |
30 |
mil |
|
Maximum PCB via count |
3 |
– |
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|
Notes: 1.See item 2 in General Memory Routing Guidelines. |
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