QDR-IV SRAM CK/DK/QK Routing and Termination

UltraScale Architecture PCB Design User Guide (UG583)

Document ID: UG583
Release Date: 2023-11-14
Revision: 1.27 English

This Figure, This Figure, and Table: QDR-IV SRAM Impedance, Length, and Spacing Guidelines for CK/DK/QK Signals define topology and routing guidelines for QDR-IV SRAM clock signals.

Figure 2-79: DK and CK Routing for QDR-IV SRAM
X-Ref Target - Figure 2-79

Figure 2-80: QK Routing for QDR-IV SRAM
X-Ref Target - Figure 2-80

Table 2-90: QDR-IV SRAM Impedance, Length, and Spacing Guidelines for CK/DK/QK Signals
Parameter	L0 (Device Breakout)	L1 (Main PCB)	L2 (DRAM Breakout)	Units
Trace type	Stripline	Stripline	Stripline	–
Clock differential impedance Z_DIFF	86±10%	76±10%	86±10%	W
Trace width/space/width	4.0/4.0/4.0	6.0/6.0/6.0	4.0/4.0/4.0	mil
Trace length	0.0~0.8/1.2⁽¹⁾	0.0~3.0	0.0~0.1	inches
Spacing in address, command, and control signals (minimum)	8.0	20	8.0	mil
Spacing to other group signals (minimum)	8.0	30	30	mil
Maximum PCB via count per signal	2			–
Notes: 1.See item 2 in General Memory Routing Guidelines.