This Figure and Table: QDR-IV SRAM Impedance, Length, and Spacing Guidelines for DQ/Address/Command Signals define topology and routing guidelines for QDR-IV SRAM DQ, address, and command signals.
|
Parameter |
L0 |
L1 |
L2 |
Units |
|---|---|---|---|---|
|
Trace type |
Stripline |
Stripline |
Stripline |
– |
|
Single-ended impedance Z0 |
50±10% |
39±10% |
50±10% |
W |
|
Trace width |
4.0 |
6.0 |
4.0 |
mil |
|
Trace length |
0.0~0.8/1.2(1) |
0.0~4.0 |
0.0~0.1 |
inches |
|
Spacing in address, command, and control signals (minimum) |
4.0 |
8.0 |
4.0 |
mil |
|
Spacing to clock signals (minimum) |
8.0 |
20 |
8.0 |
mil |
|
Spacing to other group signals (minimum) |
8.0 |
30 |
30 |
mil |
|
Maximum PCB via count |
4 (addr/cmd) 2 DQ |
– |
||
|
Notes: 1.See item 2 in General Memory Routing Guidelines. |
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