The QDR-IV SRAM interface consists of clock, control, address, command, and data signals as shown in Table: QDR-IV SRAM Interface Signal Description.
Table 2-88: QDR-IV SRAM Interface Signal Description
|
Signal Name
|
Description
|
|
Clock Signals
|
|
CK/CK#
|
Address/command clock
|
|
DK/DK#
|
Write data clock
|
|
QK/QK#
|
Read data clock
|
|
Control Signals
|
|
ZQ
|
Output impedance match
|
|
Address Signals
|
|
a[19:0]
|
Memory address bus (20:0 if using x18 data widths)
|
|
Command Signals
|
|
LD#
|
Synchronous load input
|
|
Data Signals
|
|
DQ[35:0]
|
Data bus
|
|
Other Signals
|
|
VRP
|
240W to GND
|
|
Notes:
1.Actual signal list might vary based on configuration.
|