There are two constraints requirements for each signal group in the QDR-IV SRAM interface:
•Maximum length/delay constraints
•Skew constraints
The maximum length/delay constraints are shown in Table: QDR-IV SRAM Maximum Length/Delay Constraints.
The skew constraints are listed in Table: QDR-IV SRAM Skew Constraints.
|
Signal Group |
Skew Constraints (ps) |
Skew Constraints (mil) |
|---|---|---|
|
DQ to clock (DQ to DK, DQ to QK) |
±5 |
±29 |
|
Address/command to CK |
±6 |
±35 |
|
DQ (slowest to fastest) |
2 |
12 |
|
Address/command (slowest to fastest) |
2 |
12 |
|
Clock to clock# (CK/DK/QK) |
2 |
12 |
|
CK to DK |
50 |
295 |
|
CK to QK |
50 |
295 |
|
Notes: 1.For skew specifications, refer to the General Memory Routing Guidelines items 3–8. |
||
IMPORTANT: FPGA package flight times must be included in both total length constraints and skew constraints. When minimum and maximum values are available for the package delay, use the midrange between the minimum and maximum values. Memory device package flight times do not need to be factored in because their variances have been accounted for in these guidelines.