•The clock, data, and SS lines are recommended to have matched lengths to facilitate meeting setup and hold times.
•PCB and package delay skew for I/O[3:0] and SS lines relative to CLK should be within ±50 ps.
•Keeping the clock and data lines equal provides greater immunity to undesirable setup and hold time effects.
•It is highly recommended to perform a signal integrity analysis on the clock line at the near (close to the Zynq UltraScale+ MPSoC) and far ends.
•For optimum performance, limit trace delays to less than 500 ps.
•Place 4.7 kW pull-up resistors on the HOLD, WP, and CS lines.
•Keep MIO[6] unconnected for higher FQSPICLK1 or FQSPICLK2 operating frequencies (>40 MHz). This allows the loopback feature to work properly.