It is recommended to place the RF PLLs close to the RFSoC device. The DAC RF PLLs should be placed next to the DAC side of the RFSoC while the ADC RF PLLs should be placed next to the ADC side of the RFSoC device. Simulation analysis should be performed to ensure that the clock input amplitude at the RFSoC device meets the specifications in the data sheet.
For PLLs that require pull-up resistors, ensure the resistor and decoupling capacitor layouts are symmetrical with respect to P and N. It is recommended to put the pull-up resistors and the decoupling capacitors for the buffer on the same layer as the RF PLL, typically layer one. This Figure shows a snapshot of a typical layout implementation.
