RLDRAM 3 Memory CK_P/N Clamshell Routing

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

This Figure shows the ck_p/n clamshell routing for clamshell-mounted RLDRAM 3 memories.

Figure 2-64: ck_p/n Clamshell Routing for Clamshell-mounted RLDRAM 3 Memories
X-Ref Target - Figure 2-64

Table: RLDRAM 3 Memory Clamshell Impedance, Length, and Spacing Guidelines for ck_p/n Signals shows the RLDRAM 3 memory clamshell impedance, length, and spacing guidelines for ck_p/n signals.

Table 2-75: RLDRAM 3 Memory Clamshell Impedance, Length, and Spacing Guidelines for ck_p/n Signals
Parameter	L0 (Device Breakout)	L1 (Main PCB)	L2 (DRAM Breakout)	L3 (To Term)	Units
Trace type	Stripline	Stripline	Stripline	Stripline	–
Clock differential impedance Z_DIFF	86±10%	76±10%	86±10%	76±10%	W
Trace width/space/width	4.0/4.0/4.0	6.0/6.0/6.0	4.0/4.0/4.0	6.0/6.0/6.0	mil
Trace length	0.0~0.8/1.2⁽¹⁾	0.0~3.0	0.0~0.25	0~1.0	inches
Spacing to other group signals (minimum)	8.0	30	30	20	mil
Maximum PCB via count per signal	3				–
Notes: 1.See item 2 in General Memory Routing Guidelines.