The RLDRAM 3 memory interface consists of clock, control, address, command, and data signals as shown in Table: RLDRAM 3 Memory Interface Signal Description.
Table 2-72: RLDRAM 3 Memory Interface Signal Description
|
Signal Name
|
Description
|
|
Clock Signals
|
|
ck_p/n[1:0]
|
Command and address clock
|
|
dk_p/n[3:0]
|
Write data clock
|
|
qk_p/n[7:0]
|
Read data clock (to device)
|
|
Control Signals
|
|
reset_n
|
Tie low to 4.7 kW resistor at far-end near RLD3 device
|
|
Address Signals
|
|
a[20:0]
|
Memory address bus
|
|
ba[3:0]
|
Bank address
|
|
Command Signals
|
|
cs_n
|
Chip select - works with ref_n and we_n to define command
|
|
ref_n
|
Works with cs_n and we_n to define command
|
|
we_n
|
Works with cs_n and ref_n to define command
|
|
Data Signals
|
|
dq[71:0]
|
Data bus
|
|
dm[3:0]
|
Write data mask
|
|
qvld[3:0]
|
Read data valid
|
|
Other Signals
|
|
VRP
|
240W to GND
|
|
Notes:
1.Actual signal list might vary based on configuration.
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