RLDRAM 3 Memory Routing Constraints

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

There are two constraints requirements for each signal group in the RLDRAM 3 memory interface:

Maximum delay constraints

Skew constraints

The maximum delay constraints are shown in Table: RLDRAM 3 Memory Maximum Delay Constraints.

Table 2-79:      RLDRAM 3 Memory Maximum Delay Constraints

Signal Group

Reference Figure

Maximum Delay Constraints (ps)

address/command

This Figure,
This Figure

1017

Data signals P0+L0+L1+L2

This Figure

1017

The skew constraints are listed in Table: RLDRAM 3 Memory Skew Constraints.

Table 2-80:      RLDRAM 3 Memory Skew Constraints

Signals

Skew Constraints (ps)

dq/dm to dk_p/n

±5

dq to qk_p/n

±5

qvld to qk_p/n

±5

dk_p/n to ck_p/n

±5

addr/cmd to ck_p/n

±5

Differential signals p to n

2

Notes:

1.For skew specifications, refer to the General Memory Routing Guidelines items 3–8.

 

IMPORTANT:   FPGA package flight times must be included in both total length constraints and skew constraints. When minimum and maximum values are available for the package delay, use the midrange between the minimum and maximum values. Memory device package flight times do not need to be factored in because their variances have been accounted for in these guidelines.