Recommended Clocking Options

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

The ADC and the DAC both have options to take in a direct RF sampling clock or a lower frequency reference clock to drive the internal PLLs. The built-in internal PLLs offer excellent phase noise and spurious performance and are likely to satisfy the requirements from the user application. The detailed performance of the PLL can be found in the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) [Ref 5] along with requirements for the reference clocks. Using the internal PLLs offers the most economical and highly integrated solution. In the case where very specific sampling clocking performance is required, an external RF PLL clock can be provided. Devices such as the Texas Instruments LMX259x family can be considered.

When using an external RF clock, particular care must be taken on the P to N skew of the differential input clock. This is very important if operating the DAC at near maximum sample rates greater than 9 GS/s. The P to N clock skew (electrical imbalance, not physical imbalance) presented at the BGA clock receiver balls should be of the order of lesser than 4 ps at the sample rate of interest. Due to the sensitivity and precision of this figure, AMD recommends that this figure be derived from a full 3D EM extraction of PCB. Higher P to N skews can lead to duty cycle distortion of the internal sampling clocks, which can limit the maximum achievable sample rate of the DAC. This is NOT a requirement if providing an input reference clock to the internal PLL and only for cases of providing an external RF clock at high sample rates.

In addition to P to N skew requirements on the DAC clock inputs, the duty cycle of the source clock should be kept to 49/51% when applying an RF clock input. Duty cycle on the input RF clock can again limit the achievable DAC maximum sample rates. A lower duty cycle of 48/52% can be tolerated if the DAC sample rate is lower than 9 GS/s. If the customer has difficulty in achieving the required specifications, further assistance should be requested from your local FAE.

Gen 3 RFSoC devices support a clock forwarding capability that allows either an internally generated RF clock or the external RF clock to be forwarded to other tiles. The clock should be sourced from the center two tiles and cannot be taken from outer tiles if forwarding an RF clock. If using the internal PLL, a reference rate clock can be sourced from the outer edge tiles. For more information on the rules and usage of clock forwarding, refer to Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269) [Ref 17].

If using the internal RF clock forwarding from either the external clock or internal PLL, there is a derating of 150 MHz (1.5%) of the maximum sample rate achieved without clock forwarding. This can be avoided by either using a separate RF clock input for each tile if available, or the internal PLL local to each tile.