All electrical routing constraints are defined upon the reference stackup (Table: Reference Stackup). The actual stackup might be different from this reference stackup. The related constraints such as width and spacing should be adjusted accordingly to meet target impedance and crosstalk in the design guide at reference stackup. For reference, this particular stackup results in an inner signal layer propagation time of 169.5 ps/in.
IMPORTANT: To achieve the highest memory interface performance, all the high-speed signals are recommended to be routed on the upper signal layers such as L3 and L5, as shown in This Figure, to minimize device pin field via crosstalk impact. Deeper signal layers could be used but signal routing spacing needs to take trade-offs into account with system-level signal integrity simulations.
IMPORTANT: Routing high-speed signals on lower signal layers comes with more board via coupling jitter depending on board thickness. Signal spacing in the same layer routing needs to be compromised to mitigate deep boards via crosstalk impact.
To determine system timing margins in this design following the AMD memory simulation guidelines, system designers should run system-level memory channel simulations to confirm actual timing margin in customer-specific layout practices.