Revision History

11/14/2023

1.27

Chapter 2: Removed XSR from This Figure.

Appendix A: Added XCAU7P-FCVA289 to Table: Decoupling Capacitor Recommendations for Artix UltraScale+ XC Devices.

Appendix B: Added XAZU4EV-SFVC784 to Table: VCCINT_VCU Decoupling Guidelines for Zynq UltraScale+ XA Devices.

Appendix D: Added new appendix.

05/19/2023

1.26

Chapter 1: Updated notes after This Figure, This Figure, This Figure, and This Figure.

Chapter 2: Replaced address with clock in item 4 of General Memory Routing Guidelines.

Chapter 3: Added XCZU63DR-FFVE1156, XCZU63DR-FSVE1156, XCZU64DR-FFVE1156, XCZU64DR-FSVE1156, XCZU65DR-FSVE1156, XCZU67DR-FSVE1156, XQZU65DR-FFRE1156, and XQZU67DR-FFRE1156 device-packages to Table: Maximum VCCINT Current for Zynq UltraScale+ RFSoCs.

Appendix A: Updated pin count for XCAU7P-SBVC484 in Table: Decoupling Capacitor Recommendations for Artix UltraScale+ XC Devices. Removed XQKU15P-FFRA1156 and XQKU15P-FFRE1517 from Table: Decoupling Capacitor Recommendations for Kintex UltraScale+ XC Devices. Add notes to Table: Zynq UltraScale+ MPSoC Decoupling Capacitor Recommendations (0.5 mm Pitch in UBVA494 and UBVA530 Devices) and Table: Zynq UltraScale+ MPSoC PS Decoupling Capacitor Recommendations (0.5 mm Pitch in UBVA494 and UBVA530 Devices). Added XCZU63DR-FFVE1156, XCZU63DR-FSVE1156, XCZU64DR-FFVE1156, XCZU64DR-FSVE1156, XCZU65DR-FSVE1156, and XCZU67DR-FSVE1156 to Table: Programmable Logic Rail Decoupling Guidelines for Zynq UltraScale+ RFSoCs, Table: VCCINT_AMS and ADC Decoupling Guidelines for Zynq UltraScale+ RFSoC XC Devices, and Table: DAC Decoupling Guidelines for Zynq UltraScale+ RFSoC XC Devices.

Appendix B: Corrected part and package numbers in Table: VCCINT_VCU Decoupling Guidelines for Zynq UltraScale+ XA Devices.

03/06/2023

1.25

Chapter 1: Moved all capacitor tables to Appendix A. Added Table 1-10. Added XCKU19P to Table 1-11. Added XCVU57P to Table 1-12. Added XCZU1CG and XCZU1EG to Table 1-13. Added Table 1-14.

Chapter 2: Removed ECC Connection Rules for DDR3 SDRAM section. In LPDDR4 x32 with ECC Memory Interface Signals and Connections, replaced SDP and DDP with “single-rank” and “dual-rank.”

Chapter 3: Moved decoupling guidelines to Appendix A.

Appendix A: Added new appendix.

Appendix B: Added new appendix.

Appendix C: Added new appendix.

07/27/2022

1.24

Chapter 1: Updated notes 1 and 2 in Table 1-2, Table 1-3, and Table 1-8. In Table 1-4, added 1.0 µF sub-column to V_CCINT/V_{CCINT_IO}, V_CCAUX/V_{CCAUX_IO}, and HDIO/HPIO columns, added XCAU10P-UBVA368 and XCAU15P-UBVA368, updated capacitor recommendations for V_CCINT/V_{CCINT_IO} at 100 µF, 47 µF, and 10 µF, and updated notes 1, 2, and 3. Updated notes 1, 2, and 3 in Table 1-5, Table 1-6, Table 1-7, and Table 1-10. Added Recommended Decoupling Capacitor Quantities for Zynq UltraScale+ Automotive Devices.

Chapter 2: Added ECC Connection Rules for DDR4 SDRAM and ECC Connection Rules for DDR3 SDRAM. Added L2 breakouts before and after L3 in This Figure, This Figure, This Figure, and This Figure. Changed DRAM to SRAM in This Figure.

Chapter 3: Updated notes 1 and 2 in Table 3-1.

Chapter 4: Added bullet about ensuring SD signals have a total delay of less than 1.3 ns to SD/SDIO. Added bullet about PS-GTR reference clock to list of recommendations in Table: PCB Design Checklist for PS-GTR.

Chapter 7: Updated VCCINT_IO connection and R1 for 3, -2, -1 in Table: VCCINT/VCCINT_IO/VCCBRAM Connection Matrix.

Chapter 8: In Table: MPSoC PS Voltage Matrix by Speed/Temperature Grade, changed VPS_MGTRAVCC for -3E from 0.90V to 0.85V.

04/15/2022

1.23

Chapter 1: Added XCZU1CG and XCZU1EG devices to Table 1-10. Added UBVA494 to Recommended Decoupling Capacitor Quantities for Zynq UltraScale+ Devices in UBVA494 and UBVA530 Packages.

Chapter 3: Added XQZU65DR-FFRE1156 and XQZU67DR-FFRE1156 to Table 3-1.

01/20/2022

1.22.1

Updated description of reset_n termination throughout.

01/06/2022

1.22

Chapter 1: Added V_{CC_PSTINFP}/V_{CC_PSINTLP} to Table: Step Load for Device Capacitance. Added Table 1-4. Removed V_CCINT/V_CCBRAM/V_{CCINT_IO} from column heading in Table 1-8. Added 1.0 µF capacitor recommendation for V_{CC_PSINTFP_DDR} in Table 1-13.

Chapter 2: In Table: Reference Stackup, updated L1 and L16 thickness from 2.5 to 0.6 mil. Replaced V_DD2 with V_DDQ in Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 SDP without ECC, Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 DDP without ECC, Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 Single-Rank with ECC, and Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 Dual-Rank with ECC. In Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 SDP without ECC and Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 Single-Rank with ECC, updated PCB termination at far end for CKE0. In Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 DDP without ECC and Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 Dual-Rank with ECC, updated PCB termination at far end for CKE0 and CKE1. Removed option 1 (80W termination to V_TT) from This Figure and This Figure. In Table: Routing Guidelines for HDI LPDDR4 Signals, replaced UBVA530 with FGAA530 package, added row for Top-L5-Top to blind/buried via routing, and added rows for Minimum spacing: CAC Signals, Minimum spacing: CAC Signals to CK, and Minimum spacing: CAC/CK to DQ/DQS.

Chapter 3: Added XQZU48DR-FFRE1156, XQZU48DR-FSRG1517, XQZU49DR-FSRF1760, XCZU65DR-FFVE1156, and XCZU67DR-FFVE1156 to Table 3-1. Added XCZU65DR-FFVE1156 and XCZU67DR-FFVE1156 to Table: Maximum VCCINT Current for Zynq UltraScale+ RFSoCs. Removed Table 3-5: Data Converter Bandwidth. Updated first sentence in paragraph after Table: Balun Specification Recommendations. Added paragraphs about P to N skew requirements and derating to Recommended Clocking Options. In Table: Signal Integrity Specifications for DAC/ADC Pairs and Clocks, changed column heading to Maximum Frequency, added row for CMRR under RFDC clocking, and added notes. In AC/DC Coupling Guidelines, added paragraph about AC coupling, updated second paragraph, and added note. In Table: Trace Length Matching, added comments for DAC/ADC data converters, updated comments for DAC data converters, ADC data converters and ADC clocks, and added DAC clock. Removed Figure 3-18: Analog_SYSREF Levels. Added important note to Pi Network for Improved Return Loss in Gen 1 Devices (XCZU25DR/ XCZU27DR/XCZU28DR/XCZU29DR). In SYSREF, removed bullet about Analog_SYSREF and PL_SYSREF, and added bullet about multi-chip synchronization. Added two bullets to Unused ADC & DAC Pins. Updated first two paragraphs in Power Regulation and Decoupling for ADC and DAC Supplies. Updated ADC_AVCC nominal voltage in Table: ADC and DAC Voltage Supply Specifications for Gen 3 Devices(1). Added sentence about glitches in PDN to Power Delivery Network Design for Time Division Duplex.

Chapter 4: Added bullet about 10 kW pull-up resistor to eMMC. Added bullet about interconnected JTAG chains to JTAG.

Appendix E: Added sentence about derating tables to first paragraph.

06/03/2021

1.21

Chapter 1: Added Recommended Decoupling Capacitor Quantities for Zynq UltraScale+ Devices in UBVA494 and UBVA530 Packages. In Table 1-14, added row for 1.0 µF.

Chapter 2: Added PCB Routing Guidelines for LPDDR4 Memories in High-Density Interconnect Boards.

02/12/2021

1.20

Chapter 1: Added XCKU19P to Table 1-5. Added XCVU23P-FSVJ1760 to Table 1-6. Added XCVU57P-FSVK2892 to Table 1-8. Added VU57P to Table 1-9. Updated first sentence in V_{CCINT_VCU} Plane Design and Power Delivery.

Chapter 2: Updated item 13 in General Memory Routing Guidelines. Updated first paragraph in PCB Guidelines for DDR4 SDRAM (PL and PS). Added Routing Rule Changes for Thicker Printed Circuit Boards.

Chapter 3: Added XCZU42DR to Table 3-1. Added paragraph about clock forwarding capability in Gen 3 RFSoC devices to Recommended Clocking Options. Added Table: ADC and DAC Voltage Supply Specifications for Gen 3 Devices(1). Updated Powering RFSoCs with Switch Regulators. Added Power Delivery Network Design for Time Division Duplex.

Chapter 4: Added bullet about device without DQS pin to DDR Mode (100 MHz). In SD/SDIO, added note about external pull-up resistor after fifth bullet, and added two bullets about level shifters.

Chapter 11: Replaced I/O with I/O/PSIO in Unconnected V_CCO Pins.

09/02/2020

1.19

Chapter 1: In Table 1-5, updated packages for XQKU5P and XCVU7P, added row for XCVU23P-VSVA1365, and updated note 3. In Table 1-10, updated packages for XCZU3CG, XCZU6CG, XCZU9CG, XCZU3EG, XCZU6EG, XCZU9EG, and XCZU15EG. Replaced Table 1-21: Maximum VCCINT Current for Virtex UltraScale+ Devices with Table 1-11, Table 1-12, and Table 1-13.

Chapter 2: Updated items 2 and 13 in General Memory Routing Guidelines. In Table: DDR4 SDRAM I/O Signal Description, updated address, write enable, row address strobe, column address strobe, chip select, and alert_n signals. Updated alert_n.

Chapter 3: Updated V_CCSDFEC and Migration. Added added XCZU43DR, XCZU46DR, XCZU47DR, XCZU48DR, and XCZU49DR to Table 3-1 and Table: Maximum VCCINT Current for Zynq UltraScale+ RFSoCs. In Table 3-1, removed note about connecting V_CCINT, V_CCBRAM, and V_{CCINT_IO} together for non-L speed grades. Added Maximum Current Draw for Zynq UltraScale+ RFSoCs. Added notes to Table: Trace Length Matching. Removed Table 3-8: Analog_SYSREF Requirements and Table 3-9: DC Coupling Input Parameters. Updated VCCINT_AMS nominal voltage in Table 3-11.

Chapter 4: Added note to JTAG and PCIe. Added bullets about termination and signal integrity simulation to PS Reference Clock. Added bullet about SDIO 0/1 power control signal to SD/SDIO. Added recommended capacitor values for PCIe in Table: PCB Design Checklist for PS-GTR.

Chapter 9: Updated 4.7 µF to 10 µF in Table: Decoupling for Non-2LE Devices and Table: Decoupling for -2LE Devices.

Appendix E: Updated Table: QDR II+ Q to CQ_P/N Skew Limit.

11/26/2019

1.18

Chapter 1: Table 1-6, updated existing XCVU19P-FSVA3824 and XCVU19P-FSVB3824 recommendations, and added XCVU19P-FSVA3824 and XCVU19P-FSVB3824 recommendations for thicker boards.

Chapter 2: Updated CK to DQS skew constraints in Table: LPDDR4 without ECC Skew Constraints and Table: LPDDR4 with ECC Skew Constraints.

Chapter 3: Updated all bandwidths in Table 3-5. Updated Anaren part number and bandwidth in Choosing the Appropriate Balun. Updated second paragraph in AC/DC Coupling Guidelines. Updated note in Isolation Recommendations. Removed Table 3-7: Available S-Parameter Models for ADC/DAC Channels. Updated Pi Network for Improved Return Loss in Gen 1 Devices (XCZU25DR/ XCZU27DR/XCZU28DR/XCZU29DR) heading. In Table: ADC and DAC Voltage Supply Specifications for Gen 1 and Gen 2 Devices(1), replaced LDO with VRM and updated note 4.

Chapter 11: Updated second paragraph in Unconnected V_CCO Pins.

08/29/2019

1.17

Chapter 1: Updated note 4 in Table 1-5. In Table 1-6, added XCVU19P, updated note 4, and added note 5. Updated note 4 in Table 1-7. In Table 1-8, added XCVU45P and XCVU47P, and updated note 4. Added VU45P and VU47P to Table 1-9. Removed heading for V_{CC_PSBATT} at 100 µF from Table 1-11.

Chapter 2: Added note about multiple DIMMs in DDR3/DDR4 UDIMM/RDIMM/SODIMM/LRDIMM Routing Guidelines (PL and PS). Updated DIMM labels in This Figure, This Figure, and This Figure. Updated PCB termination at far end for CS0 in Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 Single-Rank with ECC.

Chapter 4: Updated trace delay to 500 ps in fifth bullet of QSPI.

06/26/2019

1.16

Chapter 1: Updated second paragraph in Recommended PCB Capacitors per Device. Added note at end of Step Load Assumptions. Updated Table 1-2, Table 1-3, Table 1-5, Table 1-6, Table 1-9, Table 1-10, and Table 1-11. Added Table 1-7 and Table 1-8. Removed sections PCB Decoupling Capacitors for Virtex UltraScale+ 58G-Enabled Devices and PCB Decoupling Capacitors for Virtex UltraScale+ High Bandwidth Memory Devices. Added Capacitor Specifications (XC Devices). Updated capacitor values and part numbers in V_{CC_PSDDR_PLL} Supply, including This Figure. Updated 10 µF 0402 and 47 µF 0603 part numbers in Table 1-17. Removed sections Capacitor Specifications and Capacitor Consolidation Rules.

Chapter 2: Updated Table: Example Signal Group Skew Constraint and This Figure. Added VRP (PL) and ZQ (PS) to Table: DDR4 SDRAM I/O Signal Description and Table: DDR3 SDRAM Interface Signal Description. Added vias to This Figure to This Figure. Added reset_n. Removed note about pin ending in termination from Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 Dual-Rank with ECC. Added VRP to Table: RLDRAM 3 Memory Interface Signal Description, Table: QDR II+ SRAM Interface Signal Description, and Table: QDR-IV SRAM Interface Signal Description.

Chapter 3: Updated capacitance values in This Figure. Updated Table 3-1, Table 3-2, and Table 3-3. Removed Table 3-2: Programmable Logic Rail Decoupling Guidelines for L Devices.

Chapter 4: In Table: PCB Design Checklist for PS-GTR, changed filter capacitor recommendation for PS_MGTRAVCC and PS_MGTRAVTT from 4.7 µF to 10 µF.

Chapter 5: Added new chapter.

05/09/2019

1.15

Chapter 1: Updated recommended note in Step Load Assumptions. Added note 4 to Table 1-11.

Chapter 2: Added LRDIMM to DDR3/DDR4 UDIMM/RDIMM/SODIMM/LRDIMM Routing Guidelines (PL and PS), DDR3 UDIMM/RDIMM/SODIMM/LRDIMM Routing Constraints, and DDR4 UDIMM/RDIMM/SODIMM/LRDIMM Routing Constraints headings. Added CK (A/B) to DQS0/1 (A/B) to Table: LPDDR4 without ECC Skew Constraints and Table: LPDDR4 with ECC Skew Constraints.

Chapter 3: Added XCZU39DR-FFVF1760 and XCZU39DR-FSVF1760 to Table 3-1 and Table 3-2. Updated ground stitching bullet in Analog Ground to Digital Ground Connection. Updated ADC input, DAC output, and DAC clock input bandwidths in Table 3-5. In Choosing the Appropriate Balun, updated Anaren bullets and added bullet for Mini Circuits TCM2-33X+. Updated Table: Signal Integrity Specifications for DAC/ADC Pairs and Clocks. Updated Trace Routing Impedance Recommendation. Removed Figure 3-10: Ground Stitching around RFSoC Pins. Removed Table 3-8: Signal Integrity Specifications for DAC/ADC Clocks and Reference Clocks and Table 3-9: Isolation Recommendations for ADC & DAC Pairs. Added routing guidelines to Trace Routing Impedance Recommendation. Updated This Figure. Added Table: Trace Length Matching: Trace Length Matching. Added paragraph about electrical length calculation after This Figure. Removed Inter-Pair Skew section. Added device numbers to Pi Network for Improved Return Loss in Gen 1 Devices (XCZU25DR/ XCZU27DR/XCZU28DR/XCZU29DR) heading. Added paragraph about AC and DC coupling after Table 3-9. Removed Ground Plane Cutout Under Passive Components section. Updated Sample Stackup. Replaced LDO with VRM in Power Regulation and Decoupling for ADC and DAC Supplies and This Figure. Added Powering RFSoCs with Switch Regulators.

Chapter 4: Added note about PS_INIT_B to PS_INIT_B, PS_PROG_B, and PS_DONE. Updated first two bullets in PS Reset (External System Reset and POR Reset). Added note to Table: PCB Design Checklist for PS-GTR.

Appendix E: Updated table title and removed note 1 in Table: DDR3 Address/Command/Control to CK Skew Limit and Table: DDR4 Address/Command/Control to CK Skew Limit.

01/04/2019

1.14

Chapter 1: Added XQKU5P-SFRB784, XQKU5P-FFRB676, XQKU15P-FFRA1156, and XQKU15P-FFRE1517 to Table 1-5. Added XQVU3P-FFRC1517, XQVU7P-FLRA2104, XQVU7P-FLRB2104, and XQVU11P-FLRC2104 to Table 1-6. Added PCB Decoupling Capacitors for Virtex UltraScale+ 58G-Enabled Devices. In Table 1-10, added note 5, and updated Example Part Number column heading, part number for 680 µF capacitor, and note 1. Added XQZU3EG-SFRA484, XQZU3EG-SFRC784, XQZU9EG-FFRC900, XQZU9EG-FFRB1156, XQZU11EG-FFRC1156, XQZU11EG-FFRC1760, XQZU15EG-FFRC900, XQZU15EG-FFRB1156, XQZU19EG-FFRB1517, XQZU19EG-FFRC1760, XQZU5EV-SFRC784, XQZU5EV-FFRB900, XQZU7EV-FFRB900, and XQZU7EV-FFRC1156 to Table 1-10. In Table 1-14, updated suggested part number for 680 µF capacitor.

Chapter 2: Updated guidelines 12 and 13 in General Memory Routing Guidelines. Replaced V_TT with V_DDQ in PCB termination for CKE0 and CKE1 in Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 SDP without ECC, Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 DDP without ECC, Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 Single-Rank with ECC, and Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 Dual-Rank with ECC. Added note 2 to Table: LPDDR4 without ECC Skew Constraints, and note 3 to Table: LPDDR4 with ECC Skew Constraints.

Chapter 3: Added XQZU28DR-FFRE1156 and XQZU28DR-FFRG1517 to Table 3-1. Replaced “PL GPIO pins” with “dedicated clock inputs” in first paragraph of SYSREF. Added note 1 to Table 3-8. Added DAC_AVTT to second paragraph in AC/DC Coupling Guidelines. Replaced “rectangular” with “circular” in title of This Figure. Updated coupling value in Table 3-8. Added This Figure and Table 3-9. In Table: ADC and DAC Voltage Supply Specifications for Gen 1 and Gen 2 Devices(1), added note 1 and removed Maximum Current column. In Unused ADC and DAC Power Pins, removed second bullet, updated third bullet, and removed Table 3-19: Leakage Current Values for ADC and DAC Tiles.

Chapter 4: Added note about PS_PROG_B and PS_POR_B to PS_INIT_B, PS_PROG_B, and PS_DONE.

Chapter 9: Added new chapter.

Appendix E: Updated skew values in second paragraph.

08/15/2018

1.13

Chapter 1: Added description of slew rates after Table: Step Load for Device Capacitance. Added XCVU13P-FSGA2577 to Table 1-6. In Table 1-10, updated type, ESL maximum, upper ESR range, and suggested part number columns, and added a row for 0.47 µF. Updated capacitor part numbers after This Figure. Added FSVH1924, FSVH2104, and FSVH2892 packages to Table 1-21.

Chapter 2: Removed LPDDR3 and LPDDR4 routing guidelines from General Memory Routing Guidelines. Added note to Overview. Updated Table: DDR4 SDRAM Address, Command, and Control Skew Constraints, Table: DDR3 SDRAM Address, Command, and Control Skew Constraints, Table: DDR3 DIMM Address, Command, and Control Skew Constraints, Table: DDR4 DIMM Skew Constraints, Table: LPDDR4 without ECC Skew Constraints, Table: LPDDR4 with ECC Skew Constraints, and Table: LPDDR3 SDRAM Memory Skew Constraints. Added dm[9:0] to Table: DDR3 SDRAM Interface Signal Description and remove note 1. Added note about ODT pins and removed ODT0/1 from FPGA Pins column in Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 SDP without ECC, Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 DDP without ECC, Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 Single-Rank with ECC, and Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 Dual-Rank with ECC.

Chapter 3: Added -2LI to first sentence in Separate V_CCINT and V_CCBRAM/V_{CCINT_IO} (-1LI, -2LI, -2LE). Added FSVE1156, FSVG1517, FSVE1156, FSVG1517, FSVE1156, FSVG1517, and FSVF1760 packages to Table 3-1 and Table 3-2. Updated description of RF signal chain after Table: Balun Specification Recommendations. Updated guard traces bullet in Isolation Recommendations. Added This Figure, This Figure, This Figure, This Figure, and This Figure. Updated SYSREF. Added sentence about separate power supplies for ADC and DAC supplies to Power Regulation and Decoupling for ADC and DAC Supplies.

Chapter 4: Replaced VCCO_MIO0 with VCCO_PSIO[0]. Removed bullet about 2.00 kW from SPI.

04/10/2018

1.12.1

Appendix E: Removed ± sign from all table entries.

04/09/2018

1.12

Chapter 1: Added PCB Decoupling Capacitors for Virtex UltraScale+ High Bandwidth Memory Devices.

Chapter 3: Added new chapter.

Chapter 4: In last bullet of SD/SDIO, changed CMD3 to DAT3. Updated second paragraph in Unconnected V_CCO Pins.

Appendix F: Added new appendix.

Appendix G: Added DS926 and PG269 to References.

02/22/2018

1.11

Reorganized content between Chapter 1, Chapter 4, Chapter 6, and Chapter 7.

Chapter 1: Updated first paragraph in Recommended PCB Capacitors per Device and added bullet item to resource usage list. Added ideal value of 0.47 µF to Table 1-14. Added Recommended Decoupling Capacitor Quantities for UltraScale and UltraScale+ Devices, Recommended Decoupling Capacitor Quantities for Artix UltraScale+, Kintex UltraScale+, and Virtex UltraScale+ Devices, and Recommended Decoupling Capacitor Quantities for Zynq UltraScale+ Devices. Moved and updated Power Supply Consolidation Solutions for Zynq UltraScale+ MPSoCs from Chapter 7. Updated Table: Number of Power Rails for Typical Configurations for Application Requiring Full Power Domain Flexibility.

Chapter 2: Rewrote Overview. In Table: Reference Stackup, updated descriptions of L2, L4, L13, and L15 layers. In General Memory Routing Guidelines, removed description of maximum routing length in guideline 2, and updated guidelines 5, 6, 14, and 23. Added This Figure. Reversed order of PCB Guidelines for DDR3/3L SDRAM (PL and PS) and PCB Guidelines for DDR4 SDRAM (PL and PS) sections. Removed Table 2-11: PCB Guidelines for DDR4 SDRAM and Table 2-22: PCB Guidelines for DDR3 SDRAM. In Table: DDR3 SDRAM Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signals, Table: DDR3 SDRAM Impedance, Length, and Spacing Guidelines for Data Signals, Table: DDR4 SDRAM Fly-by Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signals, Table: DDR4 SDRAM Impedance, Length, and Spacing Guidelines for Data Signals, Table: Impedance, Length, and Spacing Guidelines for One-Slot DIMM Address, Command, and Control Signals to Table: Impedance, Length, and Spacing Guidelines for DIMM Data Signals, updated L0 and L1 trace lengths, and added note 2. In Table: DDR3 SDRAM Impedance, Length, and Spacing Guidelines for Clock Signals, Table: DDR4 SDRAM Impedance, Length, and Spacing Guidelines for Clock Signals, and Table: Impedance, Length, and Spacing Guidelines for DIMM Clock Signals, updated L0 and L1 trace lengths, and note 2. Updated skew constraints for signal group data to DQS in Table: DDR3 SDRAM Data Group Skew Constraints, Table: DDR4 SDRAM Data Group Skew Constraints, Table: DDR3 DIMM Data Group Skew Constraints, and Table: DDR4 DIMM Skew Constraints. Updated note after Table: DDR3 SDRAM Address, Command, and Control Skew Constraints. Added alert_n to Table: DDR4 SDRAM I/O Signal Description. Added note to Fly-by and Clamshell Topologies. Added note to Table: Allowable Mirror Pins for DDR4 SDRAM. Added alert_n. Updated This Figure. In Table: DDR4 SDRAM Clamshell Impedance, Length, Width, and Spacing Guidelines for Address/Command/Control Signals and Table: DDR4 SDRAM Clamshell Impedance, Length, Width, and Spacing Guidelines for Clock Signals, updated L0 and L1 trace lengths, and added note 1. Updated note after Table: DDR4 SDRAM Address, Command, and Control Skew Constraints, Table: DDR3 DIMM Address, Command, and Control Skew Constraints, Table: DDR4 DIMM Address, Command, and Control Skew Constraints, Table: RLDRAM 3 Memory Skew Constraints, Table: QDR II+ SRAM Skew Constraints, and Table: QDR-IV SRAM Skew Constraints. Added Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 Single-Rank with ECC. Added Signal Segment column to Table: LPDDR3 SDRAM Memory Skew Constraints. Updated L1 trace length in Table: Clamshell Routing Impedance, Length, and Spacing Guidelines for Address and Command Signals, Table: RLDRAM 3 Memory Fly-by Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signals, Table: RLDRAM 3 Memory Fly-by Impedance, Length, and Spacing Guidelines for Clock Signals to Table: RLDRAM 3 Memory Impedance, Length, and Spacing Guidelines for Data Signals, Table: QDR II+ SRAM Impedance, Length, and Spacing Guidelines for Clock and Data Signals, Table: QDR-IV SRAM Impedance, Length, and Spacing Guidelines for DQ/Address/Command Signals, and Table: QDR-IV SRAM Impedance, Length, and Spacing Guidelines for CK/DK/QK Signals. Added VREFCA and VREFDQ. Removed instances of length constraints from introductory text in RLDRAM 3 Memory Routing Constraints, including Table: RLDRAM 3 Memory Maximum Delay Constraints. Removed skew constraints (mil) column from Table: RLDRAM 3 Memory Skew Constraints. Added PCB Guidelines for LPDDR4 Memories without ECC (PS), PCB Guidelines for LPDDR4 Memories with ECC (PS), and PCB Guidelines for LPDDR3 SDRAM (PL and PS) from Chapter 4.

Chapter 4: Renamed chapter title. Removed section Design Example for x32 LPDDR4 with ECC. In CAN, changed PCB and package skew to ±100 ps. Added bullet about series resistor to eMMC. In Standard and High-Speed SDR Interfaces, updated heading and changed PCB and package skew to ±100 ps. Updated heading in HS200 (200 MHz) and High-Speed DDR Interfaces. Removed TDO from JTAG. In SDR Mode, changed PCB and package skew to ±100 ps. In DDR Mode (100 MHz), updated second bullet and added third bullet. In PS Reset (External System Reset and POR Reset), replaced VCCO_PSIO[3] with VCCO_MIO0 in first bullet, and added two new bullets. Updated first and second bullets in PS_INIT_B, PS_PROG_B, and PS_DONE. Updated fifth bullet in QSPI. Updated first bullet in Real-Time Clock. In SD/SDIO, updated first bullet, removed bullet about PCB and package delay skew, and added bullet about 10 kW pull-up resistor. In SPI, Triple Time Counter, and Watchdog Timer, changed PCB and package skew to ±100 ps.

02/22/2018

1.11
(Cont’d)

Removed Trace B section. In UART, changed MIO trace delay to 1.30 ns and removed bullet about matching TX line. In USB 2.0, updated PCB and package delays, and added bullet about 30W series resistor. Added recommendation to tie pins to ground in Table: PCB Design Checklist for PS-GTR.

Chapter 7: Renamed chapter title. Updated 7. Memory Interface PCB Routing, including Table: DDR4 SDRAM Performance in UltraScale+ FPGAs in the Presence of Migration for Single-Rank Component.

Chapter 8: Added -2E speed grade to Table: MPSoC PL Voltage Matrix by Speed/Temperature Grade. Added XCZU2EG/XCZU3EG to first sentence in 4. -3 Speed Migration. Updated note in 5. VCU Migration. Updated This Figure. Removed Figure 6-8: VCCINT_VCU Connection Options for CG/EG/EV Migration (PCB). Updated first two sentences in Example: Schematic/PCB Options to Enable VCU Migration from EV to CG/EG Devices. Removed section 7. Application Processor and Real-Time Processor Migration.

Chapter 11: Replaced “Kintex UltraScale and Virtex UltraScale FPGAs” with “UltraScale architecture-based devices.” In Table: EDA Tools for PDS Design and Simulation, updated ADS and SIwave vendors, replaced Specctraquest Power Integrity with Sigrity, and removed Speed 2000, PowerSI, PowerDC.

Appendix E: Added ± to all entries in Table: DDR3 Data to DQS Skew Limit, Table: QDR II+ D to K_P/N Skew Limit to Table: QDR II+ ADDR/CMD to CLK Skew Limit for Clock Point-to-Point and CA Fly-by, and Table: QDR II+ ADDR/CMD to CLK Skew Limit for Clock T-Branch and CA T-Branch. Updated entries in Table: DDR4 Data to DQS Skew Limit to Table: RLDRAM 3 ADDR/CMD to CK_P/N Skew Limit.

01/30/2017

1.10

Replaced “midpoint” with “midrange” throughout.

Chapter 1: Added This Equation. Added RLD1517 and RLF1924 packages for XQKU115 devices to Table 1-2. Updated V_CCINT values in Table 1-21.

Chapter 2: Updated guideline 12 in General Memory Routing Guidelines. Added note after This Figure, This Figure, and This Figure.

Chapter 7: Replaced HR I/O with HD I/O in Table 4-1. Added Migration between UltraScale and UltraScale+ FPGAs.

Chapter 4: Replaced HR I/O with HD I/O in Table 5-1. Added V_{CCINT_VCU} Decoupling Capacitor Recommendations. Added V_{CCO_PSDDR} to Table 5-3. Added description of V_{CCINT_VCU} to Video Codec Unit (EV Devices Only). Updated PCB Guidelines for DDR3 and DDR4 SDRAM. Added DQ bus width to Figure 5-8. Updated third bullet about PCB and package delay skew in SD/SDIO. Updated list of filters for PS_MGTRAVCC and PS_MGTRAVTT in Table: PCB Design Checklist for PS-GTR.

Chapter 8: Added new chapter.

Appendix E: Replaced Mb/s with MHz as units for memory component rating in Table: QDR II+ D to K_P/N Skew Limit to Table: QDR II+ ADDR/CMD to CLK Skew Limit for Clock T-Branch and CA T-Branch.

Appendix G: Added UG1085, WP482, UG580, UG1075, PG213, PG203, and PG212 to References.

11/18/2016

1.9

Chapter 1: Updated chapter title. Updated resource usage bulleted list in Recommended PCB Capacitors per Device. Added Step Load Assumptions, including Table: Step Load for Device Capacitance, and Maximum Current Draw for V_CCINT in UltraScale+ Devices. Added RBA676 and RFA1156 packages to Table 1-2.

Chapter 2: Updated guideline 14 in General Memory Routing Guidelines. Added This Figure and This Figure. Distinguished between fly-by and clamshell topology in Overview. Added CS0_n, CS1_n to Table: DDR4 SDRAM I/O Signal Description. Added Fly-by and Clamshell Topologies and Utilizing Address Mirroring to Ease Clamshell Routing. Updated first sentence in DDR4 SDRAM Address, Command, and Control Fly-by and Clamshell Topologies. Added “fly-by” to title of Table: DDR4 SDRAM Fly-by Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signals. Added This Figure, This Figure, Table: DDR4 SDRAM Clamshell Impedance, Length, Width, and Spacing Guidelines for Address/Command/Control Signals, and Table: DDR4 SDRAM Clamshell Impedance, Length, Width, and Spacing Guidelines for Clock Signals. Updated DDR4 SDRAM Data Signals Point-to-Point for Fly-by and Clamshell Configurations.

Chapter 6: Updated recommendations in 15. Power Supplies and Thermal Considerations.

Chapter 7: Updated chapter title. Added notes 4 through 7 to Table 4-1. Added XCVU9P-FSGD2104, XCVU11P-FLGD2104, and XCVU13P-FIGD2104 devices, and notes 4 through 7 to Table 4-2. Added Table: Corresponding Half-Banks and Full-Banks. Removed sentence about UltraScale+ FPGAs having stricter ESD handling requirements than UltraScale FPGAs from 10. ESD Requirements.

Chapter 4: Updated chapter title. Updated Table 5-1. Added LPDDR4 Address Copy, page 142, LPDDR4 Address Copy, page 149, and LPDDR3 Address Copy, page 161. Removed bullet about PCB and package delay skew from SD/SDIO.

07/18/2016

1.8

Chapter 1: Added note 2 to Table 1-2 and Table 1-3.

Chapter 2: Clarified guideline 5 in General Memory Routing Guidelines. Replaced CD with CK in This Figure title. Added important note before This Figure. Replaced reset_b with reset_n throughout. Updated reset_n and reset_n, including removal of Figure 2-17 and Figure 2-22. Removed note about package delay (P0) from Table: DDR3 SDRAM Data Group Skew Constraints, Table: DDR3 SDRAM Address, Command, and Control Skew Constraints, Table: DDR4 SDRAM Data Group Skew Constraints, Table: DDR4 SDRAM Address, Command, and Control Skew Constraints, Table: DDR3 DIMM Data Group Skew Constraints, Table: DDR3 DIMM Address, Command, and Control Skew Constraints, Table: DDR4 DIMM Skew Constraints, Table: DDR4 DIMM Address, Command, and Control Skew Constraints, Table: RLDRAM 3 Memory Skew Constraints, Table: QDR II+ SRAM Skew Constraints, and Table: QDR-IV SRAM Skew Constraints. Added we, ras, cas, and TEN to Table: DDR4 SDRAM I/O Signal Description. Removed L2 column from Table: Impedance, Length, and Spacing Guidelines for DIMM Clock Signals. In Table: Impedance, Length, and Spacing Guidelines for One-Slot DIMM Address, Command, and Control Signals, removed L2 column, and updated L1 parameters. Added Table: Impedance, Length, and Spacing Guidelines for Two-Slot DIMM Address, Command, and Control Signals. Replaced dm with dk/qk in Table: RLDRAM 3 Memory Impedance, Length, and Spacing Guidelines for dk and qk Signals.

Chapter 6: Added recommendation to use Delphi thermal model to 15. Power Supplies and Thermal Considerations.

Chapter 7: Removed PCI Express from UltraScale+ FPGA Migration Checklist.

Chapter 4: Added Zynq UltraScale+ MPSoCs and V_CCINT/V_{CCINT_IO} at 0.47 µF to Table 5-1. Added note 2 to Table 5-3. Added Video Codec Unit (EV Devices Only). Added reset_n to Table 5-5 and Table 5-14. Updated Figure 5-3. In Table 5-11 and Table 5-13, removed note about package delay (P0), updated skew constraints (mil), and removed CK to DQS (A)/(B) row. Updated L2 spacing to other group signals in Table 5-4 to Table 5-7, and Table 5-11. Updated Figure 5-4. Added PCB Guidelines for LPDDR3 SDRAM. Updated recommendations for PS_MGTRREF and PS_MGTRAVTT in Table: PCB Design Checklist for PS-GTR.

Appendix E: Updated second paragraph at start of appendix. Updated cells in Table: DDR3 Data to DQS Skew Limit to Table: DDR4 Address/Command/Control to CK Skew Limit, added notes to all tables, and updated titles of Table: DDR3 Address/Command/Control to CK Skew Limit and Table: DDR4 Address/Command/Control to CK Skew Limit.

04/26/2016

1.7

Chapter 2: In General Memory Routing Guidelines, updated guidelines 10 and 21, and added guidelines 11 and 23. Updated paragraph after Table: Example CK to DQS Skew Constraint. Removed DIMM from This Figure. Added introductory sentences for Figure 2-17 and This Figure. In Table: DDR3 SDRAM Interface Signal Description, updated descriptions of cke[1:0] and reset_b. Added heading to and updated reset_n. Updated introductory sentence before This Figure and This Figure. Added note 3 to Table: DDR3 SDRAM Address, Command, and Control Skew Constraints, Table: DDR4 SDRAM Address, Command, and Control Skew Constraints, and Table: DDR3 DIMM Address, Command, and Control Skew Constraints. In Table: DDR4 SDRAM I/O Signal Description, updated descriptions of cke and reset_b. Added notes about pin rules and swapping after Table: DDR3 SDRAM Interface Signal Description and Table: DDR4 SDRAM I/O Signal Description. Added ±10% to all entries for Z_DIFF in Table: DDR4 SDRAM Impedance, Length, and Spacing Guidelines for Clock Signals and Table: DDR4 SDRAM Impedance, Length, and Spacing Guidelines for Data Signals.

Chapter 6: Updated 15. Power Supplies and Thermal Considerations.

Chapter 4: Added V_{CC_PSDDR_PLL} Supply. Updated PCB Guidelines for DDR3 and DDR4 SDRAM. Updated L2 column in Table 5-5, Table 5-6, Table 5-7, Table 5-8, Table 5-9, Table 5-8, and Table 5-11. Updated signal names and connections in Figure 5-3, Figure 5-4, and Figure 5-8. Made CKE routing pull up to V_TT in Figure 5-3. Updated DQ width in Figure 5-4. Updated Table 5-11 and Table 5-14. Added channel B to ECC unit in Figure 5-3 and Figure 5-4. Made ending via pull up to V_TT in Figure 5-4. Added channel A label to Figure 5-5. Updated ECC unit in Figure 5-6. Updated trace lengths in Table 5-5 through Table 5-11. Updated L3 Z_diff in Table 5-9. Replaced DRAM with memory device in Figure 5-7 and Figure 5-8. Updated L1 spacing in Table 5-10. Updated Table 5-13. Added PCB Guidelines for the PS Interface in the Zynq UltraScale+ MPSoC.

Appendix E: Added notes to Table: DDR4 Data to DQS Skew Limit and Table: DDR4 Address/Command/Control to CK Skew Limit.

Appendix G: Added Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) to References.

02/04/2016

1.6

Chapter 1: Updated paragraph after resource usage bullets in Recommended PCB Capacitors per Device. In Table 1-2, added SFVA784 package for XCKU035 and XCKU040, and FFVA1156 package for XCKU095. Added footnote with definition of electrical inch to 0805 Ceramic Capacitor.

Chapter 2: Updated Overview. Updated note in Table: Reference Stackup. Significant revision to the General Memory Routing Guidelines section including adding Table: Example Signal to Signal Skew Constraint through Table: Example CK to DQS Skew Constraint and This Figure to This Figure. Added the Adjusting for Different Stack-Ups section. Updated cke[1:0] and reset_b descriptions in Table: DDR3 SDRAM Interface Signal Description and Table: DDR4 SDRAM I/O Signal Description. Added Figure 2-17, This Figure, Figure 2-21, and This Figure. Replaced strobe with dqs in Table: DDR3 SDRAM Impedance, Length, and Spacing Guidelines for Data Signals, Table: DDR4 SDRAM Impedance, Length, and Spacing Guidelines for Data Signals, and Table: Impedance, Length, and Spacing Guidelines for DIMM Data Signals. In Table: DDR3 SDRAM Data Group Skew Constraints, Table: DDR4 SDRAM Data Group Skew Constraints, Table: DDR3 DIMM Data Group Skew Constraints, and Table: DDR4 DIMM Skew Constraints replaced strobe with DQS and clock with CK and updated note 1. Added new rows and updated note 1 and 2 in Table: DDR3 SDRAM Address, Command, and Control Skew Constraints, Table: DDR4 SDRAM Address, Command, and Control Skew Constraints, Table: DDR3 DIMM Address, Command, and Control Skew Constraints, and Table: DDR4 DIMM Address, Command, and Control Skew Constraints. In Table: DDR3 DIMM Data Group Skew Constraints, updated CK to DQS constraints and added notes 2 and 5. In Table: DDR4 DIMM Skew Constraints, updated CK to DQS constraints and added note 2. Updated note 1 in Table: RLDRAM 3 Memory Skew Constraints, Table: QDR II+ SRAM Skew Constraints, and Table: QDR-IV SRAM Skew Constraints. Removed PCB Guidelines for LPDDR3 Memories section.

Chapter 7: In Table 4-1, removed XCKU7P in all packages, and added XCKU3P-FFVB676, XCKU3P-FFVD900, XCKU5P-SFVB784, XCKU5P-FFVA676, and XCKU5P-FFVD900. Updated packages for XCVU9P, XCVU11P, and XCVU13P in Table 4-2. Added A676 and A1156 packages to Table: UltraScale to UltraScale+ FPGA Migration Paths by Package.

Chapter 4: Added XCZU15EG to Table 5-1. In Table 5-3, replaced VCCPSGTA with PS_MGTRAVCC, VCCPSDDR with VCC_PSINTFP_DDR, and added underscores to other column headings. Moved PCB Guidelines for LPDDR4 Memories without ECC from Chapter 2 and expanded section. Added PCB Guidelines for LPDDR4 Memories with ECC.

11/24/2015

1.5

Added UltraScale+ FPGA (Chapter 7) and Zynq UltraScale+ MPSoC information (Chapter 4).

09/16/2015

1.4

Chapter 1: Added V_CCO (Bank 0) column to Table 1-2 and Table 1-3.

Chapter 2: Added QDR-IV SRAM to chapter title and Overview. In General Memory Routing Guidelines, updated second, fifth, seventh, and eighth guidelines, and added third, fourth, ninth and tenth guidelines. Updated This Figure. Added reset_b to control signals in Table: DDR3 SDRAM Interface Signal Description and Table: DDR4 SDRAM I/O Signal Description. Updated L3 trace length in Table: DDR3 SDRAM Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signals, Table: DDR3 SDRAM Impedance, Length, and Spacing Guidelines for Clock Signals, Table: DDR4 SDRAM Fly-by Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signals, Table: DDR4 SDRAM Impedance, Length, and Spacing Guidelines for Clock Signals, Table: RLDRAM 3 Memory Fly-by Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signals, Table: RLDRAM 3 Memory Fly-by Impedance, Length, and Spacing Guidelines for Clock Signals, and Table: QDR II+ SRAM Impedance, Length, and Spacing Guidelines for Address and Command Signals. Removed selected L2 breakouts from This Figure, This Figure, This Figure, This Figure, This Figure, and This Figure. Updated table title and maximum length/delay constraints column in Table: DDR3 SDRAM Total Length/Delay Constraints, Table: DDR4 SDRAM Total Length/Delay Constraints, Table: DDR3 DIMM Total Length/Delay Constraints, Table: DDR4 DIMM Total Length/Delay Constraints, Table: RLDRAM 3 Memory Maximum Delay Constraints, Table: QDR II+ SRAM Maximum Length/Delay Constraints, Table: QDR-IV SRAM Maximum Length/Delay Constraints, and Table 2-58. Added skew constraints (mil) column and added table note to Table: DDR3 SDRAM Data Group Skew Constraints, Table: DDR3 SDRAM Address, Command, and Control Skew Constraints, Table: DDR4 SDRAM Data Group Skew Constraints, Table: DDR4 SDRAM Address, Command, and Control Skew Constraints, Table: DDR3 DIMM Data Group Skew Constraints, Table: DDR3 DIMM Address, Command, and Control Skew Constraints, Table: DDR4 DIMM Skew Constraints, Table: DDR4 DIMM Address, Command, and Control Skew Constraints, Table: RLDRAM 3 Memory Skew Constraints, Table: QDR II+ SRAM Skew Constraints, Table: QDR-IV SRAM Skew Constraints, and Table 2-59. Replaced device with FPGA in DDR3 SDRAM Address, Command, and Control Fly-by Termination. Updated Table: DDR4 SDRAM Data Group Skew Constraints title. Updated Table: DDR3 DIMM Address, Command, and Control Skew Constraints title and data to strobe skew constraints. Added Table: DDR4 DIMM Address, Command, and Control Skew Constraints. Updated This Figure. Removed parenthetical comments from descriptions in Table: RLDRAM 3 Memory Interface Signal Description and Table: QDR II+ SRAM Interface Signal Description. Added “qvld to qk_p/n” row to Table: RLDRAM 3 Memory Skew Constraints. Updated This Figure. Replaced K_P/N with K and K_B in QDR II+ SRAM Clock (K, K_B, and BWS) T-Branch Routing and Termination. Replaced k_p/k_n with k/k_b in QDR II+ SRAM Clock and Data Signals (d/k/k_b) Point-to-Point Routing. Replaced cq_p/cq_n with cq/cq_b in QDR II+ SRAM Clock and Data Signals (q/cq/cq_b) Point-to-Point Routing. Added signal groups “k to k_b” and “q to q_b” to Table: QDR II+ SRAM Skew Constraints. Added signal group “ck_p to ck_n” to Table 2-59. Added PCB Guidelines for QDR-IV SRAM.

Chapter 6: Replaced pin with footprint throughout. Updated 1. Footprint Compatibility between Packages. Replaced XCVU160 with XCVU190 in Example. Added MGTRREF and MGTAVTTRCAL.

Appendix E: Added new appendix.

03/09/2015

1.3

Chapter 1: In Table 1-2, added XCKU035 and XCKU100 devices and removed note about 0402 2.2 µF capacitors. Added Table 1-3.

Chapter 2: Removed LPDDR2 throughout. Updated fourth and fifth guidelines in General Memory Routing Guidelines. Updated L0 trace length to 0.0~0.8/1.2 in Impedance, Length, and Spacing Guidelines tables. Updated L1 trace length to Address L1 + 0.25 in Table: DDR3 SDRAM Impedance, Length, and Spacing Guidelines for Clock Signals, Table: DDR4 SDRAM Impedance, Length, and Spacing Guidelines for Clock Signals, and Table: Impedance, Length, and Spacing Guidelines for DIMM Clock Signals. Updated address/command/control signal group in Table: DDR3 SDRAM Total Length/Delay Constraints, Table: DDR4 SDRAM Total Length/Delay Constraints, Table: DDR3 DIMM Total Length/Delay Constraints, and Table: DDR4 DIMM Total Length/Delay Constraints. Updated skew constraints in Table: DDR3 SDRAM Data Group Skew Constraints, Table: DDR3 SDRAM Address, Command, and Control Skew Constraints, Table: DDR4 SDRAM Data Group Skew Constraints, Table: DDR4 SDRAM Address, Command, and Control Skew Constraints, Table: DDR3 DIMM Data Group Skew Constraints, Table: DDR4 DIMM Skew Constraints, Table: RLDRAM 3 Memory Skew Constraints, and Table: QDR II+ SRAM Skew Constraints. Added note about skew specifications to Table: DDR3 SDRAM Data Group Skew Constraints, Table: DDR3 SDRAM Address, Command, and Control Skew Constraints, Table: DDR4 SDRAM Data Group Skew Constraints, Table: DDR4 SDRAM Address, Command, and Control Skew Constraints, Table: DDR4 DIMM Skew Constraints, Table: RLDRAM 3 Memory Skew Constraints, Table: QDR II+ SRAM Skew Constraints, and Table 2-59. Updated table note referring to item 5 of General Memory Routing Guidelines throughout. Updated skew constraints for “data to strobe” signal group in Table: DDR4 SDRAM Data Group Skew Constraints and Table: DDR4 DIMM Skew Constraints. Added row for differential signals to Table: RLDRAM 3 Memory Skew Constraints. Updated all trace lengths in Table: QDR II+ SRAM Impedance, Length, and Spacing Guidelines for Address and Command Signals. Updated L1 trace length to 1.0~4.0 in Table: QDR II+ SRAM Impedance, Length, and Spacing Guidelines for Clock and Data Signals. Updated This Figure. Updated title of This Figure. Removed “R = 50W” label from This Figure. Added pull-up resistor to CA line in This Figure. In Figure 2-52 and Figure 2-53, replaced V_TT with V_DDQ and changed pull-up resistance from 120W to 60W. Removed “spacing in addr/cmd/ctrl” row from Table 2-56.

Chapter 6: Added new chapter.

Chapter 11: Updated second paragraph of Input Thresholds. Updated second paragraph of V_REF Stabilization Capacitors.

Appendix G: Updated list of documents in References.

12/01/2014

1.2

Chapter 1: Removed recommendation asking customers to run their own power integrity simulations. In Table 1-2, replaced “should” with “must” in notes 1 and 2 and added note 4. Removed Table 1-2: Virtex UltraScale Devices Power Supply Decoupling Capacitors. In Table 1-14, added row for 470 µF, and updated ESL maximum and suggested part numbers for 100 µF, 47 µF, and 4.7 µF capacitors. In PCB Bulk Capacitors, added 470 µF to first paragraph and replaced niobium oxide with polymer aluminum in second paragraph.

Chapter 2: Added sentence about inner signal layer propagation time to first paragraph of Reference Stackup. Updated Thickness column in Table: Reference Stackup. Added second, fifth, and sixth guidelines and This Figure to General Memory Routing Guidelines. Replaced “length matching” with “skew” throughout. Changed units in skew constraints column from mils to picoseconds and updated notes in all skew constraints tables. Replaced “routing length” with “flight times” in Important notes after skew constraints tables. Removed DDR3 SDRAM ODT Settings and DDR4 SDRAM ODT Settings sections. Updated L0 trace length to 0~0.6/1.2 and added table note in all impedance, length, and spacing guidelines tables. Added DDR3/DDR4 UDIMM/RDIMM/SODIMM/LRDIMM Routing Guidelines (PL and PS). Replaced “depth” with “width” in RLDRAM 3 Memory Topology and Routing Guidelines for Clamshell and Fly-by Configurations. Updated maximum PCB via count to 6 in Table: Clamshell Routing Impedance, Length, and Spacing Guidelines for Address and Command Signals and Table: RLDRAM 3 Memory Fly-by Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signals. Updated L2 trace length in Table: RLDRAM 3 Memory Fly-by Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signals to Table: RLDRAM 3 Memory Impedance, Length, and Spacing Guidelines for Data Signals. Updated title of This Figure. Added This Figure. In Table: RLDRAM 3 Memory Impedance, Length, and Spacing Guidelines for Data Signals, added Z₀ parameter and removed Z_diff and differential trace row. Updated DATA IN and DATA OUT ports in This Figure. Added This Figure. Added QDR II+ SRAM Topology and Routing Guidelines for T-Branch Configuration. Removed “QDRII+ SRAM Clock (k and cq) Differential Point-to-Point Routing” section. Added QDR II+ SRAM Clock (K, K_B, and BWS) T-Branch Routing and Termination. Added clock to QDR II+ SRAM Clock and Data Signals (d/k/k_b) Point-to-Point Routing and QDR II+ SRAM Clock and Data Signals (q/cq/cq_b) Point-to-Point Routing. Removed resistor from This Figure. Updated Table: QDR II+ SRAM Skew Constraints. Removed “clock” from LPDDR3 Memory Address, Command, and Control Point-to-Point Routing. Added Important note after Table 2-59.

Chapter 10: Removed VRN from Unidirectional Topographies and Termination.

Chapter 11: Replaced “inductance” with “impedance” in This Figure.

08/28/2014

1.1

Chapter 1: Replaced 0603 capacitor with 0805 capacitor throughout. In Recommended PCB Capacitors per Device, added alternate network example, Recommended icon, and Table 1-2. Updated Table 1-2. In Table 1-2, updated body size and voltage rating of 4.7 µF capacitor and removed note 3 about ESR. Updated first paragraph in PCB Bulk Capacitors.

Chapter 2: Added new chapter.

Chapter 11: In Noise Limits, updated first paragraph and updated low-frequency variance bullet. Updated first paragraph in Role of Inductance. Updated description of tantalum capacitors in Capacitor Parasitic Inductance. Updated Capacitor Mounting Inductance. Updated second trade-off bullet in FPGA Mounting Inductance. Updated terminology in Noise Magnitude Measurement.

Appendix G: Added UltraScale Architecture GTY Transceivers User Guide (UG578) to References.

12/10/2013

1.0

Initial Xilinx release.