Routing Rule Changes for Thicker Printed Circuit Boards

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

The DDR4 routing rules provided in this chapter allow for the interface to run at the maximum supported data rates as specified in the Virtex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS923) while also assuming a maximum board thickness of 100 mil. For boards that are thicker than 100 mil, the maximum interface speed might need to be adjusted downward. See Table: DDR4 Maximum Data Rates per Board Thickness for maximum memory data rates per board thickness.

Table 2-11: DDR4 Maximum Data Rates per Board Thickness
DDR4	Board Thickness (mil)
DDR4	£ 100	101 – 145	101 – 145 + Stub-free⁽¹⁾	145 – 275
Component	See DS923	Two memory speed grades lower from data rates in DS923	See DS923	Three memory speed grades lower from data rates in DS923
1-Rank DIMM	See DS923	See DS923	See DS923	One memory speed grade lower from data rates in DS923
2-Rank DIMM	See DS923	See DS923	See DS923	One memory speed grade lower from data rates in DS923
4-Rank DIMM	See DS923	See DS923	See DS923	One memory speed grade lower from data rates in DS923
Notes: 1.Stub-free refers to alternating the routing of the signals between upper and lower layers such that long via stubs are avoided. See This Figure for an example of alternate layer routing as compared to conventional routing shown in This Figure.

Figure 2-20: Thicker PCB: Command/Address/Control Bus Conventional Routing
X-Ref Target - Figure 2-20

Figure 2-21: Thicker PCB: Command/Address/Control Bus Stub-Free Routing
X-Ref Target - Figure 2-21