SYSREF

In each Zynq\ UltraScale+\ RFSoC there is one dedicated input SYSREF pin pair located in DAC tile 0. This SYSREF signal is used for multi-tile and multi-chip channel synchronization. This differential input pair is referred to as the Analog_SYSREF. To fully implement the synchronization features in the RFSoC, an additional SYSREF signal is needed to drive into the PL fabric through a pair of dedicated clock inputs. This pair is referred to as the PL_SYSREF. It is possible to use the multi-tile sync feature even if not all available tiles in the device are being used. In such an event, DAC tile 0 should be one of the active tiles. ADC tile 0 should also be one of the active tiles if multi-tile sync for the ADCs is a requirement in the application. All DAC tiles are synchronized to DAC tile 0, and all ADC tiles are synchronized to ADC tile 0. That is why tile 0 is required to be active for the respective data converter types.

AMD recommends that the user prioritize the lower indexed tiles over the higher ones if not all tiles are to be enabled. For example, if only two tiles are used, tile 0 and tile 1 should be enabled, while tile 2 and 3 are disabled. Analog_SYSREF can also be used for synchronizing the phase of the digital up converter (DUC) numerically controlled oscillators (NCOs) and digital down converter (DDC) NCOs, respectively, in addition to synchronizing the overall delay of each tile (done with the MTS function). The NCO synchronization is a separate process from the MTS synchronization and only applicable if the fine complex mixer is used in the application. Refer to the Multi-Converter Synchronization section in Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269) [Ref 17] for the detailed theory of operations and connection diagram.

The Analog_SYSREF is internally terminated differentially at 100W. It can be used in AC coupled mode or DC coupled mode. For applications that require NCO synchronization across multiple devices, DC coupled mode is required along with the ability to generate the SYSREF signal in a pulse mode. Refer to Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269) for additional guidance. Refer to Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) [Ref 5] for further requirements.

This Figure shows the Analog_SYSREF receiver equivalent circuit. In the figure, the driver must be capable of sourcing and sinking common mode current through a 1 kW resistor. The driver must also set its own common mode bias.

For AC coupling, the SYSREF input sets the common mode voltage internally as shown in This Figure. For DC coupling, the SYSREF source driver must be capable of sourcing and sinking common mode current through the internal 1 kW resistor. The SYSREF driver must set its own common mode bias. AMD suggests using DC coupling to avoid glitches in the single shot or gapped clock scenarios.

If synchronizing ADC and DAC tiles with SYSREF, the frequency must be an integer sub-multiple of This Equation.

Equation 3-1      

An example calculation for SYSREF is shown below.

Equation 3-2      

Equation 3-3      

Equation 3-4      

Equation 3-5      

For full functionality of the synchronization features, the PL_SYSREF should meet the following requirements:

•PL_SYSREF should be the same frequency as the Analog_SYSREF.

•PL_SYSREF must be a sub-multiple of the PL frequencies that interface to the DAC and ADC FIFOs.

•PL_SYSREF and PL clock must meet setup and hold to ensure the PL clock can be used to deterministically capture the rising edge of the PL_SYSREF.

•The same clock quality (if not the same clock) should be used for the PL_SYSREF as the Analog_SYSREF. Refer to the PL GPIO electrical requirements for coupling, voltage swing, and termination.

•If the MMCM is used to generate the final PL clocks for the DAC FIFO interface and ADC FIFO interface, the 0-delay (0 phase) feature of the MMCM should be used in addition to using flip-flops to synchronize the PL_SYSREF capture as shown in the example below.

•For multi-chip synchronization, it is very important to ensure alignment of Analog_SYSREF, PL_SYSREF, PL_Ref_clk, and data converter clocks between chips to ensure a common and matched timing reference distribution to all chips.