Sample Stackup

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

This section shows a sample stackup for the top six layers of the board. The trace dimensions in the example are approximate trace geometries based on the sample stackup using a typical dielectric thickness between the signal/ground layers to achieve a 100W differential impedance. Customers are requested to run their own SI analysis to arrive at these numbers based on their specific stackup information taking manufacturing tolerances into account.

Using Isola I-Tera material with these parameters:

Pre-preg, h = 6.0 mils, DK = 3.17, 72%, 2 x 1067 MS

Core, h = 5.0 mils, DK = 3.08, 72%, 2 x 1067 MS

2 µm surface roughness for copper to minimize insertion loss

The pre-preg measures 6.0 mils before lamination. It will likely measure around 5.5 mils after lamination.