Signals and Connections for x32 Dual Channel LPDDR4 DDP without ECC

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

The required signals for a x32 dual channel LPDDR4 DDP non-ECC interface are shown in Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 DDP without ECC. The table shows which FPGA memory interface signals connect to which pins on the LPDDR4 device, along with any required termination.

Table 2-38: Signal Connection Matrix for x32 Dual Channel LPDDR4 DDP without ECC
FPGA Pins	LPDDR4 Pins	PCB Termination at Far End
Clock Signals
CK0_P CK0_N	CK_t_A CK_c_A	None
CK1_P CK1_N	CK_t_B CK_c_B	None
Address and Command Signals
A[5:0]	CA[5:0]_A	None
A[15:10]	CA[5:0]_B	None
Control Signals (CKE, CS, and ODT ⁽¹⁾)
CKE0	CKE0_A CKE0_B	160W to V_DDQ/160W to GND
CKE1	CKE1_A CKE1_B	160W to V_DDQ/160W to GND
CS0	CS0_A CS0_B	None
CS1	CS1_A CS1_B	None
	ODT_CA_A	Direct connect to V_DD2
	ODT_CA_B	Direct connect to V_DD2
Data Signals
DQ[15:0]	DQ[15:0]_A	None
DQ[31:16]	DQ[15:0]_B	None
DM0	DMI0_A	None
DM1	DMI1_A	None
DM2	DMI0_B	None
DM3	DMI1_B	None
DQS0_P DQS0_N	DQS0_t_A DQS0_c_A	None
DQS1_P DQS1_N	DQS1_t_A DQS1_c_A	None
DQS2_P DQS2_N	DQS0_t_B DQS0_c_B	None
DQS3_P DQS3_N	DQS1_t_B DQS1_c_B	None
Reset
RESET_N	RESET_n	4.7 kW to GND
Notes: 1.The FPGA ODT pins should be left unconnected. The ODT pin(s) of the memory device should be directly connected as specified in this table. 2.Each ZQ pin on the LPDDR4 devices should be individually tied to V_DDQ through a 240W resistor. 3.The ZQ pin on the FPGA should be tied to GND through a 240W resistor.